In-plane switching mode liquid cystal display device having common electrode on passivation layer
AssigneeLG. Philips LCD Co., Ltd.
InventorsSeong Moh Seo, Hyun Ho Shin, Young Jin Oh, Hyun Chang Lee, Chang Yeon Kim
Life of this patent
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Abstract
An in-plane switching mode liquid crystal display device comprises first and second substrates, a plurality of gate and data bus lines defining pixel regions and arranged on the first substrate, a plurality of data electrodes on same plane of the data bus lines these some parts are overlapped with adjacent gate bus line, a passivation layer on the data electrodes, a plurality of common electrodes on the passivation layer these some parts are overlapped with adjacent data electrodes, and a liquid crystal layer between the first and second substrates.
Claims23
An in-plane switching mode liquid crystal display device, comprising:
- a substrate;
- a plurality of gate and data bus lines arranged on the substrate defining a pixel region;
- transistors arranged at corresponding cross points of the plurality of gate and data bus lines;
- at least one data electrode connected to each one of the plurality of data bus lines, wherein a portion of the at least one data electrode overlaps with an adjacent gate bus line;
- a passivation layer formed above the transistors and the at least one data electrode;
- at least one common electrode formed above the passivation layer, wherein a portion of the at least one common electrode overlaps with the adjacent gate bus line and the at least one data electrode, such that the at least one data electrode is in a layer between the adjacent gate bus line and the at least one common electrode;
- and
- a common line coupled with the at least one common electrode.
An in-plane switching mode liquid crystal display device, comprising:
- a substrate;
- a plurality of data bus lines and a pluraltiy of gate bus lines on the substrate, the data bus lines arranged substantially perpendicular to the gate bus lines such that the data bus lines and gate bus lines define a plurality of unit pixel regions;
- a plurality of common bus lines in a layer above and substantially parallel to the plurality of gate bus lines, wherein a respective one of the common bus lines partially overlaps a respective one of the gate bus lines;
- a thin film transistor in one of the unit pixel regions adjacent an intersection of a respective one of the plurality of data bus lines and the respective one of the plurality of gate bus lines;
- a plurality of first data electrodes in the unit pixel region substantially parallel to the data bus lines;
- a second data electrode in the unit pixel region, the second data electrode substantially perpendicular to the first data electrodes and connecting respective ends of the first data electrodes, the second data electrode being partially by and in a layer between the respective one of the common bus lines and the respective one of the gate bus lines;
- and
- a plurality of common electrodes in the unit pixel region extending from the respective one of the common bus lines across the unit pixel region to another common bus line that partially overlaps another of the gate bus lines.
Dependencies are inferred from the claim text.