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US 6,445,419 B1Granted
Image processing apparatus
AssigneeNEC Corporation
InventorTatsuya Sanpei
Life of this patent
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Abstract
An image processing apparatus includes a decoding circuit block decoding a coded image input signal specified by NTSC system with a frame rate of the NTSC system and writing a decoded image signal in an image memory as image data, and a display-image producing circuit block producing a display image data by reading the image data from the image memory with a frame rate specified by PAL system, thereby achieving the frame rate transformation from the NTSC system to PAL system, and at this time, carrying out the skipping for display at every one extent field.
Claims11
An image processing apparatus, comprising:
- a decoding circuit block decoding a coded image signal of MPEG specified by an NTSC system with a frame rate of the NTSC system and writing a decoded image signal of the MPEG in an image memory as MPEG image data;
- and
- a display-image producing circuit block performing a frame rate transformation from the NTSC system to a PAL system with the MPEG image data, skipping a field at intervals of some fields, when reading the MPEG image data from the image memory with a frame rate of the PAL system, and thereby producing MPEG image data;
- and
- an inverted line correcting filter for correcting image mutilation caused by inverted lines, the MPEG image data, in which a field at intervals of some fields is skipped, read out from the image memory is inverted in order of a top field and a bottom field.
2 more elements
Dependencies are inferred from the claim text.