Serialized mapped memory configuration for a video graphics chip

A memory system comprising:

• memory containing data for a plurality of controllers;
• a multiplexer operatively coupled to the memory and operative to select data for transfer with the memory over a first bus at a first rate;
• and
• a multichannel serializer, operatively coupled between the multiplexer and a plurality of controllers through a plurality of second buses wherein each of the second buses is associated with a different channel, having a serializer for each of a plurality of second buses wherein each of the serializers transfers data associated with a channel at a second rate to a corresponding controller and wherein the multichannel serializer obtains data from the multiplexer at a third rate over a same size bus as the first bus;
• wherein the memory includes a plurality of banks of memory blocks and an address decoder per bank and wherein the second rate is faster than the first rate and wherein a rate at which data is obtained from the multiplexer by each serializer is the same and is slower than the first and second rate;
• such that the multiplexer and multichannel serializer facilitate multiple controller access to the memory and wherein the memory, multiplexer and multichannel serializer are located on a same circuit die.