US 6,445,321 B2 · Hybrid low-pass sigma-delta modulator

Abstract

A hybrid loop filter includes an integrator having an input and an output wherein the output forms an output of the hybrid loop filter, a plurality of transconductance amplifiers having an input and an output wherein each output of the plurality of transconductance amplifiers is coupled to the input of the integrator, a switched capacitor low pass chain having an input and a plurality of branches wherein each of the plurality of branches is coupled to the input of a separate one of said plurality of transconductance amplifiers, and a feedthrough branch having an input and an output wherein the input is coupled to the input of the switched capacitor low pass chain to form an input of said hybrid loop filter, and the output is coupled to the input of a separate one of the plurality of transconductance amplifiers.

Drawings

Drawings are temporarily unavailable. Open the PDF at USPTO

Drawings

Claims53

Dependent claims

A hybrid loop filter comprising:

an integrator for absorbing an error current from an amplified signal and for generating a capacitance charging current at an output of said hybrid loop filter;
a plurality of transconductance amplifiers for generating said amplified signal from a plurality of signals to said integrator;
a switched capacitor low pass chain for integrating charges from a first set of capacitor switched by a second set of capacitor and for generating said plurality of signals to said plurality of transconductance amplifiers;
and
a feedthrough branch for feeding through an input signal of said hybrid loop filter to said plurality of transconductance amplifiers.

2 more elements

A hybrid loop filter comprising:

an integrator for absorbing an error current from a first and a second amplified signal and for generating a capacitance charging current at a first and second output of said hybrid loop filter;
a plurality of transconductance amplifiers for generating said first and said second amplifier signal from a first and second plurality of signals to said integrator;
a first switched capacitor low pass chain for integrating charges from a first set of capacitor switched by a second set of capacitor and for generating said first plurality of signals to said plurality of transconductance amplifiers;
a second switched capacitor low pass chain for integrating charges from a third set of capacitor switched by a fourth set of capacitor and for generating said second plurality of signals to said plurality of transconductance amplifiers;
a first feedthrough branch for feeding through a first input signal of said hybrid loop filter to said plurality of transconductance amplifiers;
and
a second feedthrough branch for feeding through a second input signal of said hybrid loop filter to said plurality of transconductance amplifiers.

4 more elements

A hybrid loop filter comprising:

an integrator for absorbing an error current from a first and a second amplified signal and for generating a capacitance charging current at a first and second output of said hybrid loop filter;
a plurality of transconductance amplifiers for generating said first and said second amplified signal from a first and second plurality of signals to said integrator;
a first switched capacitor low pass chain for integrating charges from a first set of switched capacitor and for generating said first plurality of signals to said plurality of transconductance amplifiers;
a second switched capacitor low pass chain for integrating charges from a second set of switched capacitor and for generating said second plurality of signals to said plurality of transconductance amplifiers;
a first feedthrough branch for feeding through a first input signal of said hybrid loop filter to said plurality of transconductance amplifiers;
and
a second feedthrough branch for feeding through a second input signal of said hybrid loop filter to said plurality of transconductance amplifiers.

4 more elements

Dependencies are inferred from the claim text.

Description5,766 words

Summary2,641 words

#1. Field of the Invention

#The present invention relates to techniques for analog-to-digital (A/D) conversion. More particularly, the present invention relates to techniques for A/D conversion using a delta-sigma modulator.

#2. The Prior Art

Brief description of the drawings22 figures

#FIG. 1 is a block diagram of a sigma-delta A/D modulator having either an active or passive loop filter as is known in the art.

#FIG. 2A is a schematic diagram of a simplified active discrete-time loop filter employed in an A/D modulator as is known in the art.

#FIG. 2B is a schematic diagram of a simplified active continuous-time loop filter employed in an A/D modulator as is known in the art.

Detailed description2,535 words

#Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.

#According to the present invention, a loop filter 100 that is a hybrid of purely active and purely passive loop filter techniques is employed in a sigma-delta A/D modulator 102 as illustrated in FIG. 3. In the loop filter 100 according to the present invention, elements of a passive switched capacitor network and elements of an active continuous-time loop filter implement a loop filter 100 permits the use of a low resolution comparator 104, even when the A/D modulator order is greater than 2. An example of such a low resolution comparator is a dynamic comparator which requires no bias current. Further, in the loop filter according to the present invention, the mixing down to the baseband of distortion, quantization noise and clock jitter sensitivity as is commonly found in an active time-continuous loop filter technique is effectively reduced.

#In FIG. 4A, according to the present invention, a first embodiment of the loop filter 100-1 is illustrated that includes a feedthrough branch 108, a switched capacitor low pass chain 110 having a plurality of stages, a transconductance amplifier stage 112 having a plurality of transconductance amplifiers, and an integrator 114. In the loop filter 100-1, the feedthrough branch 108 and each of the stages in the switched capacitor low pass chain 110 is coupled to one of the plurality of transconductance amplifiers in the transconductance amplifier stage 112. Each combination of either the feedthrough branch 108 or a switched capacitor low pass chain 110 stage with a transconductance amplifier forms a branch of the loop filter 100-1.

Facts

Application

09/801,013Filed 6 Mar 2001 · continuation in part

Priority

5 Apr 1999

Published

US 2001/0009403 A126 Jul 2001

Granted

3 Sep 2002

Term ended

5 Apr 2019

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification9 codes

H03H 11/04
Multiple-port networks: frequency selective two-port networks
H03H 19/004
Networks using time-varying elements, e.g. N-path filters: switched capacitor networks
H03M 3/344
Characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a…: by…
H03H 11/0422
Frequency selective two-port networks: using transconductance amplifiers, e.g. gmC filters

Family

Application09/286,261Parent of this continuation · filed 5 Apr 1999

Application09/703,501Parent of this continuation-in-part · filed 31 Oct 2000

Application09/703,501Parent of this continuation

US 6,163,287 AParent of this continuation

US 2001/0009403 A1Published application

US 6,466,146 B1Related patent

US 6,445,321 B2This patent

From the US filing history. Foreign family members aren’t listed.

Hybrid low-pass sigma-delta modulator

Life of this patent

Hybrid low-pass sigma-delta modulator

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims53

Description5,766 words

Drawings

Classification9 codes

Life of this patent

Description5,766 words