Circuit topology for better supply immunity in a cascaded Gm/Gm amplifier

Abstract

There is disclosed an amplifier comprising: 1) a plurality of cascaded NMOS differential amplifier stages, wherein a first one of the plurality of cascaded NMOS differential amplifier stages is coupled to at least one input signal; 2) a PMOS differential amplifier stage having a first input coupled to a first NMOS differential output of a last one of the plurality of cascaded NMOS differential amplifier stages and a second input coupled to a second NMOS differential output of the last cascaded NMOS differential amplifier stage, wherein the PMOS differential amplifier comprises a first diode-connected PMOS load transistor having a gate and a drain connected to ground and a second diode-connected PMOS load transistor having a gate and a drain connected to ground; and 3) an output differential amplifier stage comprising: a) load transistors comprising a third PMOS transistor having a gate and a drain connected together and a source connected to a power supply rail and a fourth PMOS transistor having a gate coupled to the third PMOS transistor gate and a source connected to the power supply rail; and b) a differential transistors pair comprising a first NMOS transistor having a gate coupled to a source of the first diode-connected PMOS load transistor and a drain coupled to a drain of the third PMOS transistor and a second NMOS transistor having a gate coupled to a source of the second diode-connected PMOS load transistor and a drain coupled to a drain of the fourth PMOS transistor.

Dependencies are inferred from the claim text.