Flip-flop circuit

A flip-flop circuit comprising:

• a pair of latch circuits, each said pair of latch circuits including a push-pull circuit input stage and a hold circuit output stage, the pair of latch circuits being cascade-connected as a master latch and a slave latch so as to be operable under control of a clock signal from a clock line,
• wherein the input stage of each latch circuit comprises two pairs of nMOS transistors or nMOSTs with push-pull data inputted thereto, each said two pairs comprising two serially-connected nMOS or nMOSTs, said two pairs connected in parallel, said parallel-connected two pairs being connected at a first parallel connection point to a first nMOST having a clock signal inputted thereto at a gate, said first nMOST additionally connected to a positive supply voltage, said parallel-connected two pairs being connected at a second parallel connection point to a second nMOST having the clock signal inputted thereto at a gate, said second nMOST additionally connected to a ground.

A flip-flop circuit comprising:

• a pair of latch circuits including a push-pull circuit input stage and a hold circuit output stage, the pair of latch circuits being cascade-connected as a master latch and a slave latch so as to be operable under control of a clock signal from a clock line,
• wherein the input stage of each latch comprises a first input of two serially-interconnected nMOSTs and a second input of two serially-interconnected nMOSTs, each of said first input and said second input receiving push-pull data inputted thereto, each of said first input and said second input being respectively connected in series between a positive supply voltage and a ground, each of said first input and said second input connecting respectively to said hold circuit output stage via an nMOST having a gate controlled by the clock line.