Apparatus and method for accelerating initial lock time of delayed locked loop

An apparatus for accelerating an initial lock time of DLL (Delayed Locked Loop) which removes skew between an external synchronization clock signal and an internal clock signal, comprising:

• means for generating a reference clock signal based on the external synchronization clock signal;
• means for applying a unit delay time and a multiple unit delay time to the reference clock signal and for comparing phases of the reference clock signal, a unit delayed reference clock signal and a multiple unit delayed reference clock signal with a phase of the internal clock signal;
• means for selecting an amount of delay time based on a comparison result;
• means for delaying the reference clock signal by the amount of delay time based on a selected amount of delay time;
• and
• means for generating a modeled delay clock signal corresponding to a delayed reference clock signal and for providing the modeled delay clock signal with said means for applying a unit delay and a multiple unit delay time.

A method for accelerating an initial lock time of DLL (Delayed Locked Loop) which removes skew between an external synchronization clock signal and an internal clock signal, comprising the steps of:

• a) receiving a reference clock signal and an internal clock signal;
• b) comparing the reference clock signal with the internal clock signal and determining an amount of delay time between the two clock signals;
• c) reducing the amount of delay time by one unit delay if the amount of the delay time is larger than a predetermined value;
• d) increasing the amount of delay time by one unit delay or a number of unit delay time if the amount of the delay time is smaller than the predetermined value, wherein the step d) includes:
• d1) generating a first clock model which is delayed by the unit delay time in comparison with the internal clock signal;
• d2) determining whether the first clock model is faster than the reference clock signal;
• d3) generating a second clock model which is delayed by a predetermined number of unit delay time in comparison with the first clock model if the first clock model is faster than the reference clock signal;
• d4) shifting a delay chain to a direction in order to increase the amount of delay time by the unit delay time of the internal clock signal if the first clock model is faster than the reference clock signal;
• and
• d5) shifting a delay chain to a direction in order to increase the amount of delay time by one more unit delay time than the predetermined number of unit delay time of the internal clock signal if the first clock model is slower than the reference clock signal;
• and
• e) repeating said steps a) to d) until a phase difference between the reference clock signal and the internal clock signal is smaller than the unit delay.

An apparatus for accelerating an initial lock time of DLL (Delayed Locked Loop) which removes skew between an external synchronization clock signal and an internal clock signal, comprising:

• means for generating a reference clock signal based on the external synchronization clock signal;
• means for applying a unit delay time and a multiple unit delay time to the reference clock signal and for comparing phases of the reference clock signal, a unit delayed reference clock signal and a multiple unit delayed reference clock signal with a phase of the internal clock signal;
• means for selecting an amount of delay time based on a comparison result;
• means for delaying the reference clock signal by the amount of delay time based on a selected amount of delay time;
• and
• means for generating a modeled delay clock signal corresponding to a delayed reference clock signal and for providing the modeled delay clock signal with said means for applying a unit delay and a multiple unit delay time.