Digital clock multiplier and divider with output waveform shaping

A variable clocking circuit for generating an output clock signal having a plurality of active edges from a reference clock signal having a plurality of active edges;

• the circuit comprising:
• a variable oscillator configured to generate the output clock signal;
• a first clock divider circuit coupled to the variable oscillator and configured to divide the output clock signal by a multiplier M to generate a feedback clock signal;
• a phase comparator coupled to the first clock divider circuit and configured to receive the reference clock signal and the feedback clock signal and to provide a phase comparator output signal;
• and
• a fine tuning controller coupled to the variable oscillator and to receive the phase comparator output signal, and configured to selectively insert delays in the output clock signal,
• wherein the fine tuning controller comprises:
• an up/down counter;
• and
• a delta-sigma circuit coupled to the up/down counter.

A variable clocking circuit for generating an output clock signal having a plurality of active edges from a reference clock signal having a plurality of active edges;

• the circuit comprising:
• a variable oscillator configured to generate the output clock signal;
• a first clock divider circuit coupled to the variable oscillator and configured to divide the output clock signal by a multiplier M to generate a feedback clock signal;
• a phase comparator coupled to the first clock divider circuit and configured to receive the reference clock signal and the feedback clock signal and to provide a phase comparator output signal;
• and
• a fine tuning controller coupled to the variable oscillator and to receive the phase comparator output signal, and configured to selectively insert delays in the output clock signal,
• wherein the output clock signal has an output clock frequency approximately equal to the multiplier M times a reference clock frequency of the reference clock signal, and
• wherein the variable oscillator comprises a variable delay line having a base delay unit and the variable clocking circuit further comprises a delay line register coupled to the variable delay line and configured to contain a delay value.

A method for generating an output clock signal from a reference clock signal, wherein the output clock signal has a output clock frequency approximately equal to a multiplier M times a reference clock frequency of the reference clock signal, the method comprising:

• creating a feedback clock signal from the output clock signal by dividing the output clock signal by M;
• comparing a feedback frequency of the feedback clock signal with the reference clock frequency;
• configuring a variable delay line with a base delay unit and a delay value in base delay units to control a period of the output clock signal;
• and
• selectively increasing a subset of clock periods of the output clock within a concurrence period to shape a waveform of the output clock signal.