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US 6,445,231 B1Granted
Digital dual-loop DLL design using coarse and fine loops
AssigneeMicron Technology, Inc.
InventorsR. Jacob Baker, Feng Lin
Life of this patent
Estimating the term…
Abstract
A dual-loop digital delay locked loop (DLL) is provided. The DLL includes a coarse loop to produce a first delayed signal and provides a wide frequency lock range. The DLL further includes a fine loop connected to the coarse loop to produce a second delayed signal and provides a tight locking. This dual-loop architecture can provide robust operation and tight synchronization over a wide range of delay variations.
Claims34
A delay locked loop system comprising:
- a coarse loop to produce a first delayed signal, the coarse loop including
- a delay range and including:
- a phase detector;
- a shift register connected to the phase detector, the shift register including a plurality of register cells;
- a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements;
- and
- a fine loop connected to the coarse loop to receive the first delay signal to produce a second delayed signal, the fine loop having a delay range, wherein the delay range of the fine loop is substantially smaller than the delay range of the coarse loop.
4 more elements
A delay locked loop system comprising:
- a first input node to receive an input signal;
- a second input node to receive a feedback signal;
- a coarse loop connected to the first and second input nodes to receive the input and feedback signals to produce a first delayed signal, wherein the first delay and feedback signals have a skew, the coarse loop including:
- a phase detector connected to the first and second input nodes;
- a shift register connected to the phase detector, the shift register including a plurality of register cells;
- a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements;
- and
- a fine loop connected to the first and second input nodes and the coarse loop to receive the input, feedback and first delayed signals to produce a second delayed signal, the second delayed and feedback signals having a skew that is smaller than the skew between the first delayed and feedback signal.
5 more elements
A delay locked loop system comprising:
- an input node to receive an input signal;
- a forward path connected to the input node, the forward path having a first delay locked loop circuit and a second delay locked loop circuit, wherein the first delay locked loop circuit has a first delay range and the second delay locked loop circuit has a second delay range, and wherein the forward path produces a delayed signal, wherein the first delay locked loop circuit including:
- a phase detector;
- a shift register connected to the phase detector, the shift register including a plurality of register cells;
- a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements;
- and
- a feedback path connected to the forward path to delay the delayed signal to produce a feedback signal, the feedback signal being fed back to the forward, wherein the forward path applies variable amounts of delay to the input signal until the input signal and the feedback signal are synchronized.
4 more elements
A delay locked loop system comprising:
- an input node to receive a clock signal;
- a coarse loop comprising:
- a phase detector connected to the input node;
- a shift register connected to the phase detector, the shift register including a plurality of register cells;
- a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements, wherein the delay cells are connected to the input node to receive the clock signal to produce a first delayed signal, wherein the first delayed signal and the clock signal has a first skew;
- a fine loop connected to the coarse loop to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the clock signal have a second skew, wherein the second skew is substantially smaller than the first skew;
- and
- a delay model circuit connected to the fine loop to delay the second delayed signal to produce a feedback signal.
5 more elements
A memory device comprising:
- a main memory;
- an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal;
- and
- a delay locked loop system connected to the output circuit, the delay locked loop system comprises:
- a coarse loop to produce a first delayed signal, the coarse loop including a first delay range and including:
- a phase detector;
- a shift register connected to the phase detector, the shift register including a plurality of register cells;
- a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements;
- a fine loop connected to the coarse loop to receive the first delay signal to produce a second delayed signal, the fine loop having a second delay range, wherein the second delay range is substantially smaller than the first delay range;
- and
- a delay model circuit connected to the fine loop to delay the second delayed signal to produce a strobe signal.
8 more elements
A memory device comprising:
- a main memory;
- an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal;
- and
- a delay locked loop system connected to the output circuit, the delay locked loop system comprising:
- an input node to receive an input signal;
- a coarse loop connected to the input node to receive the input signal to produce a first delayed signal, wherein the first delayed signal and the input signal has a first skew, the coarse loop including:
- a phase detector connected to the first and second input nodes;
- a shift register connected to the phase detector, the shift register including a plurality of register cells;
- a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements;
- a fine loop connected to the coarse loop to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the input signal has a second skew, wherein the second skew is substantially smaller than the first skew;
- and
- a delay model circuit connected to the fine loop to delay the second delayed signal to produce a strobe signal.
9 more elements
A memory device comprising:
- a main memory;
- an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal;
- and
- a delay locked loop system connected to the output circuit, the delay locked loop system comprising:
- an input node to receive a clock signal;
- a coarse loop comprising:
- a phase detector connected to the input node;
- a shift register connected to the phase detector, the shift register including a plurality of register cells;
- a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements, wherein the delay cells are connected to the input node to receive the clock signal to produce a first delayed signal, wherein the first delayed signal and the clock signal has a first skew;
- a fine loop connected to the coarse loop to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the clock signal have a second skew, wherein the second skew is substantially smaller than the first skew;
- and
- a delay model circuit connected to the fine loop to delay the second delayed signal to produce a feedback signal.
9 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device comprising:
- a main memory;
- an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal;
- and
- a delay locked loop system connected to the output circuit, the delay locked loop system comprises:
- a coarse loop to produce a first delayed signal, the coarse loop including a first delay range and including:
- a phase detector;
- a shift register connected to the phase detector, the shift register including a plurality of register cells;
- a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements;
- a fine loop connected to the coarse loop to produce a second delayed signal, the fine loop having a second delay range, wherein the second delay range is substantially smaller than the first delay range;
- and
- a delay model circuit connected to the fine loop to delay the second delayed signal to produce a strobe signal.
11 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device comprising:
- a main memory;
- an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal;
- and
- a delay locked loop system connected to the output circuit, the delay locked loop system comprising:
- an input node to receive an input signal;
- a coarse loop connected to the input node to receive the input signal to produce a first delayed signal, wherein the first delayed signal and the input signal has a first skew, the coarse loop including:
- a phase detector connected to the first and second input nodes;
- a shift register connected to the phase detector, the shift register including a plurality of register cells;
- a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements;
- a fine loop connected to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the input signal has a second skew, wherein the second skew is substantially smaller than the first skew;
- and
- a delay model circuit connected to the fine loop to delay the second delayed signal to produce a strobe signal.
12 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device comprising:
- a main memory;
- an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal;
- and
- a delay locked loop system connected to the output circuit, the delay locked loop system comprising:
- an input node to receive a clock signal;
- a coarse loop comprising:
- a phase detector connected to the input node;
- a shift register connected to the phase detector, the shift register including a plurality of register cells;
- a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements, wherein the delay cells are connected to the input node to receive the clock signal to produce a first delayed signal, wherein the first delayed signal and the input signal has a first skew;
- a fine loop connected to the coarse loop to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the clock signal has a second skew, wherein the second skew is substantially smaller than the first skew;
- and
- a delay model circuit connected to the fine loop to delay the second delayed signal to produce an output signal.
12 more elements
Dependencies are inferred from the claim text.