Programmable digital phase lock loop

A system for analyzing a reference signal representing bits of data and comprising a series of pulses propagating at a fixed rate and each having a rising edge, the system comprising:

• a) a digital phase lock loop having an input to receive the reference signal and providing an output bit clock signal, the bit clock signal being related to the reference signal in a manner providing information on the times at which data can be extracted from the reference signal;
• b) a source of base clock signals connected to the digital phase lock loop and having a frequency many times that of the bit clock signal;
• and
• c) a configuring component operatively associated with the digital phase lock loop to program selected parameters of the bit clock signal, wherein the configuring component contains a program for determining the pulse width time of the output bit clock signal and at least one offset time between the output bit clock signal and the reference signal.

A system for analyzing a reference signal representing bits of data and comprising a series of pulses propagating at a fixed rate and each having a rising edge, the system comprising:

• a) a digital phase lock loop having an input to receive the reference signal and providing an output bit clock signal, the bit clock signal being related to the reference signal in a manner providing information on the times at which data can be extracted from the reference signal;
• b) a source of base clock signals connected to the digital phase lock loop and having a frequency many times that of the bit clock signal;
• and
• c) a configuring component operatively associated with the digital phase lock loop to program selected parameters of the bit clock signal, wherein the configuring component contains a program for adjusting the period of the output bit clock signal in the event that the period is not an integral multiple of the period of the base clock signal.

A method for providing an output pulse signal which is synchronized to an input reference pulse signal and which free runs at a programmed rate in the absence of the reference pulse signal comprising:

• a) providing a digital phase lock loop having an input to receive the reference pulse signal, a source of base clock signals, a configuring component operatively associated therewith and an output to provide the output pulse signal;
• b) utilizing the configuring component to program the pulse width time of the output pulse signal and at least one offset time between the output pulse signal and the input reference pulse signal;
• and
• c) causing the digital phase lock loop to provide the output pulse signal synchronized to the rising edges of the pulses of the input reference pulse signal and in the absence of a pulse of the reference signal to provide the output pulse signal free running at a programmed rate.

A method for providing an output pulse signal which is synchronized to an input reference pulse signal and which free runs at a programmed rate in the absence of the reference pulse signal comprising:

• a) providing a digital phase lock loop having an input to receive the reference pulse signal, a source of base clock signals, a configuring component operatively associated therewith and an output to provide the output pulse signal;
• b) utilizing the configuring component to provide an adjustment in the period of the output pulse signal in the event that the period is not an integral multiple of the period of the base clock signal;
• and
• c) causing the digital phase lock loop to provide the output pulse signal synchronized to the rising edges of the pulses of the input reference pulse signal and in the absence of a pulse of the reference signal to provide the output pulse signal free running at a programmed rate.

A method for initializing a programmable digital phase lock loop to provide an output pulse signal which is synchronized to an input reference pulse signal and which free runs at a programmed rate in the absence of the reference pulse signal comprising:

• a) providing input calling parameters for the programmable digital phase lock loop including the period of a base clock signal, the period of the output pulse signal, the percent of the period of the output pulse signal that the output pulse is high and the position in time of the rising edge of the input reference pulse signal;
• b) computing the number of ticks of the base clock of the digital phase lock loop in the period of the output pulse signal to obtain a result in the form of a whole number and a fractional remainder if any;
• c) utilizing the input calling parameters to compute the times of the offset between the rising edge of the input reference pulse signal and the rising edge of the output pulse signal, of the width of the output pulse signal and of the offset between the trailing edge of the output pulse and the next expected rising edge of the reference pulse signal;
• d) utilizing the fractional remainder when present to create an adjustment in the period of the output pulse signal to minimize drift error;
• and
• e) writing configuration values obtained from the foregoing initializing to the programmable digital phase lock loop.

In a telephony network including a telephony switch and one or more emulated digital telephony devices having operations to be commanded and monitored by said telephony switch:

• a) an analog/digital converter coupled to said telephony switch having an output to provide a pulse data signal including commands for said one or more digital telephony devices provided by said telephony switch and having an input to receive a signal including information on the state of said one or more digital telephony devices to be sent to said telephony switch;
• b) a programmable digital phase lock loop having an input to receive the pulse data signal and having an output to provide a bit clock signal synchronized to the rising edge of the pulse and which free runs at a programmed rate in the absence of the rising edge of the pulse data signal, the bit clock signal having programmed parameters including pulse width and offset from the pulse data signal;
• c) a microprocessor operatively connected to said programmable digital phase lock loop;
• d) a receive component having inputs to receive the pulse data signal and the bit clock signal and operatively connected to said microprocessor to convert serial data obtained from the pulse data signal into parallel data for use by said microprocessor to determine operations commanded by said telephony switch for said one or more digital telephony devices;
• and
• e) a transmit component operatively connected to said microprocessor and having an input to receive the bit clock signal and an output connected to the input of said analog/digital converter to convert parallel data obtained from said microprocessor to serial data for transmission to said telephony switch to provide information on the state of said one or more digital telephone devices.