US 6,445,229 B1 · Digital phase lock loop

Abstract

A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

Claims14

Dependent claims

A digital phase lock loop circuit for receiving a first signal and generating a second signal having a desired frequency which is a predetermined multiple of said first signal, comprising:

a variable delay chain;
and
control circuitry coupled to said variable delay chain for:
generating a third signal having a frequency at least partially dependent upon a delay provided by said variable delay chain;
for dividing said third signal by a settable factor to generate said second signal;
and for adjusting said delay provided by said variable delay chain.

3 more elements

Dependencies are inferred from the claim text.

Digital phase lock loop

Life of this patent

Digital phase lock loop

Life of this patent

Abstract

Claims14