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US 6,445,228 B1Granted
Programmable even-number clock divider circuit with duty cycle correction and optional phase shift
AssigneeXilinx, Inc.
InventorAndy T. Nguyen
Life of this patent
Estimating the term…
Abstract
A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown on the output node. The set and reset control signals are also provided to a keeper circuit that maintains a value placed on the output node.
Claims16
A clock divider circuit, comprising:
- a clock input terminal;
- a clock output terminal;
- a state machine having an input terminal coupled to the clock input terminal, and further having set and reset output terminals;
- a keeper circuit having an output terminal coupled to the clock output terminal;
- a pullup circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the set output terminal of the state machine, and an output terminal coupled to the clock output terminal;
- and
- a pulldown circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the reset output terminal of the state machine, and an output terminal coupled to the clock output terminal.
4 more elements
A programmable clock divider circuit, comprising:
- a clock input terminal;
- a clock output terminal;
- a programmable control circuit having an input terminal coupled to the clock input terminal, and further having set and reset output terminals;
- a pullup circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the set output terminal of the programmable control circuit, a set output terminal, and a clock output terminal coupled to the clock output terminal;
- a pulldown circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the reset output terminal of the programmable control circuit, a reset output terminal, and a clock output terminal coupled to the clock output terminal;
- and
- a keeper circuit having an output terminal coupled to the clock output terminal.
4 more elements
Dependencies are inferred from the claim text.