Output circuit converting an internal power supply potential into an external supply potential in a semiconductor apparatus
AssigneeNEC Corporation
InventorKazutaka Taniguchi
Life of this patent
Estimating the term…
Abstract
A three-state buffer circuit has a pull-up side transistor and a pull-down side transistor connected in series between an external power supply potential and a grounding voltage. An output signal is outputted from a node between the pull-up and pull-down transistors. A first level shift circuit is connected to a gate of the pull-up side transistor, and a voltage of a data signal is converted from an internal power supply potential lower than an external power supply potential to the external power supply potential. A second level shift circuit is connected to a gate of the pull-down side transistor, and a voltage of a data signal is converted from the internal power supply potential to the external power supply potential.
Claims8
An output circuit comprising:
- a three-state buffer circuit having a pull-up side transistor and a pull-down side transistor connected in series between an external power supply potential and a grounding voltage;
- an output terminal connected to a node between the pull-up side transistor and the pull-down side transistor buffer circuit;
- a first level shift circuitry connected to a gate of the pull-up side transistor, the first level shift circuitry converting a voltage of an input signal from an internal power supply potential lower than the external power supply potential to the external power supply potential;
- a second level shift circuitry connected to a gate of the pull-down side transistor, the second level shift circuitry converting a voltage of a data signal from the internal power supply potential to the external power supply potential;
- a signal change detecting circuit for detecting a change of the input signal;
- and
- a delay circuitry for delaying an output signal of this signal change detecting circuit to output to the first and second level shift circuitry a signal for controlling an output of an output circuit to be active or inactive, wherein, when the control signal is in a first state, either one of the pull-up side transistor and pull-down side transistor is turned OFF, causing the output terminal to enter a high impedance, and when the control signal is in a second state, a signal according to “high” or “low” of the data signal is outputted to the output terminal.
An output circuit comprising:
- a three-state buffer circuit having a pull-up side transistor and a pull-down side transistor connected in series between an external power supply potential and a grounding voltage;
- an output terminal connected to a node between the pull-up side transistor and the pull-down side transistor;
- a first level shift circuitry connected to a gate of the pull-up side transistor, the first level shift circuitry converting a voltage of a data signal from an internal power supply potential lower than the external power supply potential to the external power supply potential;
- a second level shift circuitry connected to a gate of said pull-down side transistor, the second level shift circuitry converting a voltage of the data signal from an internal power supply potential to the external power supply potential;
- a signal change detecting circuit for detecting a change of the data signal;
- a delay circuitry for delaying an output signal of this signal change detecting circuit to output to the first and second level shift circuitry a signal for controlling an output of an output circuit to be active or inactive;
- a NAND circuit to which the data signal and the control signal are inputted;
- an NOR circuit to which the data signal and an inverting signal of the control signal are inputted;
- and
- an inverter connected between an output end of the second level shift circuitry and a gate of the pull-down side transistor, wherein, when the control signal is in a first state, either one of the pull-up side transistor and pull-down side transistor is turned OFF, causing the output terminal to enter a high impedance, and when the control signal is in a second state, a signal according to “high” or “low” of the input signal is outputted to the output terminal.
Dependencies are inferred from the claim text.