US 6,445,222 B1 · Data output circuit with reduced output noise

Abstract

A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.

Claims3

Dependent claims

A data output circuit for providing a signal of a logic corresponding to a logic of an input signal applied to an input node to an output node, comprising:

drive element means for driving said output node to a potential level corresponding to a first logic level of said input signal according to said input signal, and
control means for increasing driving capability of said drive element means as a potential of the signal of said output node approaches said potential level;
wherein said drive element means includes:
a first drive element coupled between the output node and a power node supplying a first potential, for driving said output node to said potential level in response to said input signal, and
a second drive element coupled in a parallel with said first drive element between said output node and said power node;
and
said control means includes:
delay means coupled to receive said input signal, for delaying transition of said input signal from a second logic level to the first logic level, and
variable drive means coupled to receive an output signal of said delay means, for activating said second drive means in response to the output signal of said delay means, said variable drive means including limiting means for progressively increasing an operating current flowing through said variable means in accordance with the potential of the signal of said output node approaching said potential level.

6 more elements

Dependencies are inferred from the claim text.

Data output circuit with reduced output noise

Life of this patent

Data output circuit with reduced output noise

Life of this patent

Abstract

Claims3