US 6,445,215 B1 · Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same

Abstract

A logic circuit performs a predetermined logic operation by supplying charge to an external load or pulling out charge therefrom according to a combination of the states of a plurality of externally inputted binary signals. The logic circuit includes a first transistor for supplying charge through an output terminal to the external load and a second transistor for pulling out the charge from the load through the output terminal. One of the first and second transistors is constituted by a MOS field-effect transistor having a drain connected to the output terminal. The MOS field-effect transistor has a source receiving an inverse signal inverse to a signal combined for logic operation with an input signal inputted to a gate of the MOS field-effect transistor. The number of the series transistors is reduced, resulting in an increase of the current capacity and in a reduction of the layout area. Adjacent ones of the logic circuits have a common source diffusion layer so that the load capacitance with respect to the inverse signal can be significantly reduced, thus enabling the high speed operation.

Claims2

Dependent claims

A semiconductor integrated circuit comprising a decoder circuit provided on a chip, said decoder circuit having an array of a plurality of logic circuits performing a predetermined logic operation by supplying charge to an external load or pulling out charge therefrom according to a combination of states of a plurality of externally inputted binary signals, each of said logic circuits comprising:

at least a first transistor means having a drain;
and
at least a second transistor having a gate receiving a first input signal and a drain forming a common node with said drain of said first transistor means,
said second transistor comprising a MOS field-effect transistor,
said MOS field-effect transistor having a source receiving an inverse signal inverse to a second signal combined for logic operation with said first input signal inputted to said gate of said MOS field-effect transistor,
said common node being an output of said logic circuit and directly connected to an inverter having a CMOS transistor structure for outputting an output signal, whereby, with said inverter, said logic circuit comprises a basic unit,
said MOS field-effect transistor being arranged such that the adjacent ones of said logic circuits share a source diffusion layer.

4 more elements

Dependencies are inferred from the claim text.

Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same

Life of this patent

Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same

Life of this patent

Abstract

Claims2