FPGA lookup table with NOR gate write decoder and high speed read decoder

For a programmable logic device including interconnect resources and a plurality of configurable logic blocks, a lookup table comprising:

• a plurality of memory cells;
• means for generating a select signal corresponding to one of the plurality of memory cells in response to a plurality of input signals received from the interconnect resources;
• and
• means for selectively writing data from the interconnect resources to the memory cell in response to the select signal.

A lookup table comprising:

• a plurality of memory cells each for storing a data bit;
• a write decoder for selecting one of the memory cells to receive a data bit, the write decoder comprising a plurality of logic gates, one logic gate for each of the memory cells, each of the logic gates decoding a different combination of input signals to address its corresponding memory cell;
• and
• a read decoder for selecting one of the memory cells to provide a data bit, the read decoder comprising a multiplexer being controlled by the input signals to select one of the memory cells.

A method for accessing a memory cell in a lookup table of a programmable logic device, the programmable logic device including interconnect resources for transmitting a plurality of input signals and data signals to the lookup table, the method comprising:

• during a memory write operation, generating a select signal in response to the plurality of input signals, the select signal being transmitted on a first select terminal of a plurality of select terminals in response to a unique set of the plurality of input signals;
• during the memory write operation, selectively passing the data signal to a selected memory circuit of a plurality of memory circuits in response to the select signal, wherein each of the plurality of memory circuits is connected to an associated one of the plurality of select terminals;
• and
• during a memory read operation, transmitting the data signal from the selected memory circuit to the interconnect resources in response to the unique set of the plurality of input signals.