US 6,445,205 B1 · Method of testing integrated circuits

Abstract

An integrated circuit which allows for ease of testing thereof, and a method of such testing. The integrated circuit includes a linear shift register without feedback, which converts signals on a bus into a serial bitstream. The integrated circuit has an output pin connected to the linear shift register to receive the serial bitstream thereon. The method of testing the chip includes supplying test inputs to the chip, reading the serial bitstream data during the test from an output pin of the integrated circuit, and comparing the output data in a test device with an expected bitstream. The signals on the bus under investigation can be monitored continually throughout the test. In the event that a fault is discovered, the test can be terminated much more quickly than when using a device which requires the test to be completed before any data can be read out.

Claims18

Dependent claims

A method of testing an integrated circuit comprising:

an internal bus, having a plurality of lines;
a linear shift register, having its inputs connected to respective lines of the bus, and adapted to convert signals on the lines of the bus into a serial bitstream;
and
an output pin, connected to the linear shift register and adapted to receive the serial bitstream thereon, and the method comprising:
supplying test inputs to the integrated circuit;
on the integrated circuit, converting signals on the internal bus thereof into the serial bitstream;
reading the serial bitstream from the output pin of the integrated circuit;
and
in a test device, comparing the read bitstream with a known bitstream.

6 more elements

Dependencies are inferred from the claim text.

Method of testing integrated circuits

Life of this patent

Method of testing integrated circuits

Life of this patent

Abstract

Claims18