Damascene metallization process and structure

A device comprising:

• a substrate with a first conductor layer pattern;
• a first dielectric layer above the substrate, with a plurality of vias formed in the first dielectric layer in the pattern of the first conductor layer;
• a first metallization layer filling the plurality of vias;
• an etch stop layer, comprising a dielectric material, above the first dielectric layer, having a pattern substantially similar to a second conductor layer pattern;
• a second dielectric layer above the first dielectric layer and the etch stop layer, the second dielectric layer and the etch stop layer being formed from materials having different etching properties such that an etch of the second dielectric layer may stop on the etch stop layer;
• a plurality of grooves in the second dielectric layer in the second conductive layer pattern;
• and
• a second metallization layer filling the plurality of grooves in the second dielectric layer.

A semiconductor device, comprising:

• a first dielectric layer;
• an etch stop layer above the first dielectric layer and below a metallization layer, the etch stop layer comprising a dielectric and having a pattern substantially similar to a second conductor layer pattern, the etch stop layer being absent from a via region, the via region formed in the first dielectric layer and the via region connecting the metallization layer to a first conductor layer;
• a second dielectric layer above the first dielectric layer, the second dielectric layer and the etch stop layer being formed from materials having different etching properties such that an etch of the second dielectric layer may stop on the etch stop layer;
• a plurality of grooves in the second dielectric layer;
• and
• the metallization layer formed by an in-laid process, and being in-laid in a single step into said grooves and filling the via region.