US 6,445,069 B1Granted

Electroless Ni/Pd/Au metallization structure for copper interconnect substrate and method therefor

AssigneeFlip Chip Technologies, L.L.C.

InventorsJamin Ling, Dave Charles Stepniak

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Abstract

A nickel/palladium/gold metallization stack is formed upon connection pads of integrated circuits at the wafer level through an electroless plating method. The metallization stack can be formed over copper or aluminum interconnect pads; the lower nickel layer bonds securely to the copper or aluminum interconnect pads, while the intermediate palladium layer serves as a diffusion barrier for preventing the nickel from out-diffusing during subsequent thermal cycles. The upper gold layer adheres to the palladium and readily receives a variety of interconnect elements, including gold bumps, gold wire bonds, solder bumps, and nickel bumps. The electroless plating process permits connection pads to be formed using fine geometries, and allows adjacent connection pads to be formed within 5 micrometers of each other.

Claims23

Dependent claims

An integrated circuit structure comprising in combination:

a. a semiconductor wafer having an upper surface, the semiconductor wafer having a plurality of identical die formed therein, each of the identical die having a plurality of semiconductor devices formed therein upon the surface of the semiconductor wafer;
b. a patterned layer of interconnect metal formed upon the upper surface of the semiconductor wafer for electrically interconnecting the plurality of semiconductor devices formed within each such die, said patterned layer of interconnect metal including connection pads for making electrical connection to circuitry external to the semiconductor wafer;
c. a patterned layer of nickel plated over each connection pad for mechanically and electrically bonding to the interconnect metal forming such connection pad, the patterned layer of nickel being in direct contact with the underlying connection pads;
d. a patterned layer of palladium plated over the patterned layer of nickel above each connection pad for preventing the nickel from diffusing outwardly through the palladium during subsequent heating cycles;
and
e. a patterned layer of gold plated over the patterned layer of palladium above each connection pad to facilitate the joinder of such connection pad with a connection element.

3 more elements

A process for forming connection pads on a plurality of integrated circuit die formed in a semiconductor wafer, the semiconductor wafer having an upper surface, each of the integrated circuit die having a plurality of semiconductor devices formed therein upon the surface of the semiconductor wafer, said process including the steps of:

a. forming a patterned layer of interconnect metal upon the upper surface of the semiconductor wafer for electrically interconnecting the plurality of semiconductor devices formed within each such integrated circuit die, said patterned layer of interconnect metal including connection pads for making electrical connection to circuitry external to the semiconductor wafer;
b. following step a., forming a patterned layer of nickel by electroless plating over each connection pad for mechanically and electrically bonding to the interconnect metal at each such connection pad, the patterned layer of nickel being in direct contact with the underlying connection pads;
c. following step b., forming a patterned layer of palladium by electroless plating over the patterned layer of nickel above each connection pad for preventing the nickel from diffusing outwardly through the palladium during subsequent heating cycles;
and
d. following step c., forming a patterned layer of gold by electroless plating over the patterned layer of palladium above each connection pad to facilitate the joinder of such connection pad with a connection element.

2 more elements

Dependencies are inferred from the claim text.