Semiconductor integrated circuit device and manufacturing method thereof

A semiconductor integrated circuit device having a first and second circuit regions on a main surface of an SOI substrate, said SOI substrate including a supporting layer, an insulating layer formed on said supporting layer, and a semiconductor region formed on said insulating layer, said semiconductor integrated circuit device comprising:

• (a) a first wide insulating isolation trench surrounding said first circuit region and arriving at said insulating layer;
• (b) a second wide insulating isolation trench surrounding said second circuit region and arriving at said insulating layer;
• (c) an intermediate region extending between said first and second wide insulating isolation trenches;
• (d) a first wiring resistor for connecting said first circuit region and said intermediate region;
• and
• (e) a second wiring resistor for connecting said second circuit region and said intermediate region.

A semiconductor integrated circuit device having a first and second circuit regions on a main surface of an SOI substrate, said SOI substrate including a supporting layer, an insulating layer formed on said supporting layer, and a semiconductor region formed on said insulating layer, said semiconductor integrated circuit device comprising:

• (a) a first insulating isolation trench surrounding said first circuit region and arriving at said insulating layer, and a second insulating isolation trench surrounding said first insulating isolation trench and arriving at said insulating layer;
• (b) a third insulating isolation trench surrounding said second circuit region and arriving at said insulating layer, and a fourth insulating isolation trench surrounding said third insulating isolation trench and arriving at said insulating layer;
• (c) an intermediate region extending between said second and fourth insulating isolation trenches;
• (d) a first wiring for connecting said first circuit region and a first isolating region which is defined by said first and second insulating isolation trenches, and a second wiring for connecting said first isolating region and said intermediate region;
• and
• (e) a third wiring for connecting said second circuit region and a second isolating region which is defined by said third and fourth insulating isolation trenches, and a fourth wiring for connecting said second isolating region and said intermediate region.

A semiconductor integrated circuit device having a first and second circuit regions on a main surface of an SOI substrate, said SOI substrate including a supporting layer, an insulating layer formed on said supporting layer, and a semiconductor region formed on said insulating layer, said semiconductor integrated circuit device comprising:

• (a) a first insulating isolation trench surrounding said first circuit region and arriving at said insulating layer, and a second insulating isolation trench surrounding said first insulating isolation trench and arriving at said insulating layer;
• (b) a third insulating isolation trench surrounding said second circuit region and arriving at said insulating layer, and a fourth insulating isolation trench surrounding said third insulating isolation trench and arriving at said insulating layer;
• (c) an intermediate region extending between said second and fourth insulating isolation trenches;
• (d) a first connecting portion for connecting said first circuit region and a first isolating region which is defined by said first and second insulating isolation trenches, and a second connecting portion for connecting said first isolating region and said intermediate region;
• and
• (e) a third connecting portion for connecting said second circuit region and a second isolating region which is defined by said third and fourth insulating isolation trenches, and a fourth connecting portion for connecting said second isolating region and said intermediate region.

A semiconductor integrated circuit device having a first and second circuit regions on a main surface of an SOI substrate, said SOI substrate including a supporting layer, an insulating layer formed on said supporting layer, and a semiconductor region formed on said insulating layer, said semiconductor integrated circuit device comprising:

• (a) a plurality of insulating isolation trenches surrounding said first circuit region and arriving at said insulating layer;
• (b) a plurality of insulating isolation trenches surrounding said second circuit region and arriving at said insulating layer;
• (c) an intermediate region extending between an outermost insulating isolation trench among said plurality of insulating isolation trenches surrounding said first circuit region and an outermost insulating isolation trench among said plurality of insulating isolation trenches surrounding said second circuit region;
• (d) a resistor element connected between said first circuit region and said intermediate region in parallel with said plurality of insulating isolation trenches;
• and
• (e) a resistor element connected between said second circuit region and said intermediate region in parallel with said plurality of insulating isolation trenches.