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US 6,445,054 B1Granted
Semiconductor device
AssigneeDynex Semiconductor Limited
InventorsTatjana Traijkovic, Florin Udrea, Gehan Anil Joseph Amaratunga
Life of this patent
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AssigneeDynex Semiconductor Limited
InventorsTatjana Traijkovic, Florin Udrea, Gehan Anil Joseph Amaratunga
Estimating the term…
A semiconductor device comprises an active area with a voltage termination structure located adjacent to the active area at an edge portion of the device. The edge portion comprises a substrate region (12) of a first semiconductor type. The voltage termination structure comprises at least one first termination region (11) of a second semiconductor type, the or each first termination region having at least one of either second and third termination regions (11a, 11b) of third and fourth semiconductor types located at substantially opposing edges thereof. The second and third termination regions (11a, 11b) respectively have a higher semiconductor doping concentration than the edge portion substrate region (12) and a lower semiconductor doping concentration than the first termination region(s) (11).
A semiconductor device comprising an active area with a voltage termination structure located adjacent to the active area at an edge portion of the device, the edge portion comprising a substrate region of a first semiconductor type, wherein the voltage termination structure comprises at least one first termination region of a second semiconductor type, said at least one first termination region having second and third termination regions of third and fourth semiconductor types located at substantially opposing edges thereof, the second and third termination regions respectively having a higher semiconductor doping concentration than the edge portion substrate region and a lower semiconductor doping concentration than said at least one first termination region.
A semiconductor device according to any preceding claim, wherein the three termination regions are provided in the region of an upper surface of the edge portion substrate region.
A semiconductor device according to any preceding claim, wherein the second and third termination regions of the voltage termination structure are implanted into the edge portion substrate region.
A semiconductor device according to any preceding claim, wherein a passivation layer is provided over the upper surface of the edge portion substrate region.
A semiconductor device according to any preceding claim, wherein a channel stopper is provided at an extreme edge of the edge portion substrate region, adjacent to the upper edge of the substrate region.
A semiconductor device according to any preceding claim, wherein the edge portion substrate region is formed of an n-type semiconductor material, and the or each first termination region is formed of a p-type semiconductor material.
A semiconductor device according to any preceding claim, wherein the device performs as a diode, a DMOSFET, a DMOS, IGBT, a MOSFET, a trench IGBT, or an MOS controllable power device.
A semiconductor device comprising an active area with a voltage termination structure located adjacent to the active area at an edge portion of the device, the edge portion comprising a substrate region of a first semiconductor type, wherein the voltage termination structure comprises at least one first termination region of a second semiconductor type, said at least one first termination region having a second termination region of a third semiconductor type located at an edge thereof, said at least one second termination region respectively having a higher semiconductor doping concentration than the edge portion substrate region and a lower semiconductor doping concentration than said at least one first termination region.
Dependencies are inferred from the claim text.