Semiconductor configuration having trenches for isolating doped regions

Abstract

A semiconductor configuration includes a substrate having a first conduction type. A transistor configuration is disposed at the substrate and is formed from at least one field-effect transistor having at least two doped regions embedded in the substrate and at least one gate electrode. The regions have a second conduction type, are disposed between the transistor configuration and the substrate edge, and extend from the substrate surface into the substrate and surround the transistor configuration. At least two adjacent insulating trench regions are disposed between the regions and extend from the substrate surface into the substrate for isolating the doped regions from one another. The trenches may have a smaller depth than the doped regions. A method for fabricating a semiconductor configuration includes providing a substrate having a first conduction type and producing regions in the substrate by introducing a dopant. The regions have a second conduction type. They extend from the surface of the substrate into the substrate and are isolated from one another in the substrate. A trench is produced at the boundary of each one of the regions facing a respective other one of the regions. Each trench has a depth greater than a depth of the respective at least two regions after introducing the dopant but less than a desired depth of the regions. The dopant is outdiffused to a desired depth greater than the depth of each respective trench. Each trench is filled by forming an insulating layer therein.

Dependencies are inferred from the claim text.