Memory cell arrangement and process for manufacturing the same
AssigneeSiemens Aktiengesellschaft
InventorsFranz Hofmann, Josef Willer, Hans Reisinger, Paul Werner von Basse, Wolfgang Krautschneider
Life of this patent
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Abstract
A number of memory cell lines insulated from one another and that respectively comprise a first doped region and a second doped region between which a gate dielectric, which contains a material with charge carrier traps and a number of gate electrodes. The spacing of neighboring gate electrodes is smaller than the dimensions of the gate electrodes. The information is stored by introduction of charge carriers into the gate dielectric. The gate electrodes are preferably manufactured with the assistance of a spacer technique.
Claims6
A memory cell arrangement in which a number of memory cell lines are arranged in a semiconductor substrate, neighboring memory cell lines being insulated from one another, the memory cell lines comprising:
- a first doped region corresponding to a source/drain region arranged at a first end of each of the memory cell lines;
- a second doped region corresponding to a source/drain region arranged at a second end of each of the memory cell lines;
- a gate dielectric arranged between each of the first and second doped regions on a principle surface of the semiconductor substrate, the gate dielectric containing a material having charge carrier traps;
- and
- a plurality of gate electrodes arranged next to one another and on the principle surface of the semiconductor substrate between the first and second doped regions, wherein, a spacing between neighboring gate electrodes is less than the dimensions of the neighboring gate electrodes in a direction parallel to the connecting memory cell lines between the first and second doped regions.
Dependencies are inferred from the claim text.