US 6,445,042 B1Granted

Method and apparatus for making MOSFETs with elevated source/drain extensions

AssigneeAdvanced Micro Devices, Inc.

InventorsBin Yu, Judy Xilin An

Life of this patent

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Abstract

An improved semiconductor device, such as a MOSFET with raised source/drain extensions on a substrate with isolation trenches etched into the surface of the substrate . The device has thin first dielectric spacers on the side of a gate and gate oxide and extend from the top of the gate to the surface of the substrate. Raised source/drain extensions are placed on the surface of a substrate, which extend from the first dielectric spacers to the isolation trenches. Thicker second dielectric spacers are placed adjacent to the first dielectric spacers and extend from the top of the first dielectric spacers to the raised source/drain extensions. Raised source/drain regions are placed on the raised source/drain extensions, and extend from the isolation trenches to the second dielectric spacers. The semiconductor device has very shallow source drain extensions which result in a reduced short channel effect.

Claims7

Dependent claims

A semiconductor device, comprising:

a substrate having an upper surface;
shallow trench isolations formed in the substrate;
a gate oxide formed on the upper surface of the substrate, the gate oxide having a first side adjacent the upper surface of the substrate and a second side opposite the first side;
a gate formed on the gate oxide, the gate having a first side adjacent the second side of the gate oxide and a second side opposite the first side at a top of the gate;
first dielectric spacers formed on the sides of the gate, the first dielectric spacers having a fist side adjacent the gate and a second side opposite the first side, and the first dielectric spacers hang a width in a range of 150 Å to 200 Å;
partially-raised source/drain extensions with a first side adjacent the upper surface of the substrate and a second side opposite the first side, the partially-raised source/drain extensions extending from the first dielectric spacers to the respective shallow trench isolations;
second dielectric spacers with a first side adjacent the first dielectric spacers and a second side opposite the first side, the second dielectric spacers extending from the second side of the partially-raised source/drain extensions to the top of the gate;
second raised source/drain regions, formed by implanted dopants in a second semiconductor layer, with a first side adjacent the second side of the partially-raised source/drain extensions, the second raised source/drain regions extending from the second dielectric spacers to the respective shallow trench isolations;
and
ultra-shallow source/drain implant junctions beneath the upper surface of the substrate, the ultra-shallow source/drain implant junctions extending from the respective shallow trench isolations to the gate oxide for reducing a short channel effect.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/687,992Filed 13 Oct 2000 · division
Priority: 15 Jun 1999
Granted: 3 Sep 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
G01N 21/9501
Characterised by the material or shape of the object to be examined: semiconductor wafers
G01R 31/307
Using electron beams: of integrated circuits
H01J 37/21
Details: means for adjusting the focus