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US 6,445,032 B1Granted
Floating back gate electrically erasable programmable read-only memory(EEPROM)
AssigneeInternational Business Machines Corporation
InventorsArvind Kumar, Sandip Tiwari
Life of this patent
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Abstract
A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.
Claims25
A semiconductor memory, comprising:
- a plurality of transistors, each said transistor including:
- a first gate having an oxide, and a channel;
- and
- a back-plane including a floating gate memory structure and a second gate and an oxide thereover, said second gate formed opposite to the channel of said transistor, said second gate comprising a back-plane gate, said back-plane gate being selectively contactable without an insulating layer therebetween;
- and
- a common conducting substrate extending substantially an entire length of multiple ones of said plurality of transistors,
- wherein a thickness of said oxide of said back-plane is separately scalable from an oxide of said first gate of said transistor,
- wherein a memory device of said semiconductor memory is realized when said back-plane gate is unconnected, said memory device assuming one of a charged and a discharged state, and
- wherein a logic device of said semiconductor memory is realized when said back-plane is directly contacted to form a bottom gate.
6 more elements
A backplane transistor, comprising:
- a first gate having an oxide and a channel, forming a transistor;
- a back-plane, formed opposite to said channel, forming a floating gate region for storing different states of memory and including an oxide, the back-plane being isolated to function as a connectable gate, said back-plane being selectively contactable without an insulating layer therebetween;
- and
- a common conducting substrate extending substantially an entire length of said transistor and an adjacent transistor,
- wherein a thickness of said oxide of said connectable gate is separately scalable from a thickness of said oxide of said first gate of said transistor,
- wherein a memory device is realized when said back-plane is unconnected and said states of memory assume one of a charged and a discharged state, and
- wherein a logic device of said memory device is realized when said back-plane is directly contacted to form a bottom gate.
4 more elements
A memory including a plurality of transistors, comprising:
- a buried connectable gate;
- a top gate having an oxide, thereby forming a transistor having a transistor channel;
- and
- a common conducting substrate extending substantially an entire length of multiple ones of said plurality of transistors,
- wherein leakage from the connectable gate is decoupled through an injection oxide from that of controlling a transistor channel of said memory,
- wherein said connectable gate is combined with a back-plane, thereby allowing the top gate and said oxide of said top gate to be scalable according to a size of said memory, said back-plane being selectively contactable without an insulating layer therebetween,
- wherein a memory device is realized when said back-plane is unconnected and said memory assumes one of a charged and a discharged state, and
- wherein a logic device of said memory is realized when said back-plane is directly contacted to form a bottom gate.
5 more elements
A memory system including a back-plane, comprising:
- a plurality of transistors, each of said transistors including a control gate and a transistor channel;
- a floating gate memory structure opposite to the control gate and beneath the transistor channel, said floating gate memory structure combined with a back-gate formed on the back-plane, said back-plane being selectively contactable without an insulating layer therebetween;
- and
- a common conducting substrate extending substantially an entire length of multiple ones of said plurality of transistors,
- wherein a memory device is realized when said back-plane is unconnected and a memory assumes one of a charged and a discharged state, and
- wherein a logic device of said memory system is realized when said back-plane is directly contacted to form a bottom gate.
3 more elements
Dependencies are inferred from the claim text.