Semiconductor device having a memory cell with a plurality of active elements and at least one passive element

A semiconductor device comprising:

• a memory cell having a plurality of active elements and at least one passive element, wherein:
• the plurality of active elements comprising the memory cell comprises field effect transistors having three terminals which comprise two diffusion layers forming a source or drain and a gate, or four terminals which comprise two diffusion layers forming a source or drain, a gate, and a substrate or a layer which includes an area at which channel is formed,
• the passive element comprising the memory cell comprises a capacitor having an insulating layer between a first electrode and a second electrode,
• the active elements comprising the memory cell include at least a transistor having a function of writing data and a transistor having a function of reading data,
• the memory cell comprises two field effect transistors and one capacitor, a first field effect transistor comprises an N-channel type or P-channel type, and a second field effect transistor comprises an N-channel type or P-channel type, and
• the memory cell is configured by a second diffusion layer terminal of the first field effect transistor, the second electrode of the capacitor, and a gate electrode terminal of the second field effect transistor connected together and, further, the first electrode of the capacitor is connected to a word line, a first diffusion layer terminal of the first field effect transistor is connected to a bit line, a gate terminal of the first field effect transistor is connected to a control gate line, a first diffusion layer terminal of the second field effect transistor is connected to the bit line, and a second diffusion layer terminal of the second field effect transistor is connected to a predetermined power supply terminal.