Semiconductor device and manufacturing method thereof
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
Estimating the term…
A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.
A semiconductor device including a pnpn structure in which main current flows between first and second main surfaces sandwiching an intrinsic or a first conductivity type semiconductor substrate, comprising:
Dependencies are inferred from the claim text.