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US 6,445,001 B1Granted
Semiconductor device with flip-chip structure and method of manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorAkito Yoshida
Life of this patent
Estimating the term…
Abstract
A semiconductor device has a plurality of input/output terminals formed on the inner region on a semiconductor substrate, and a plurality of die testing terminals formed on the peripheral region on the semiconductor substrate, and the input/output terminals and the die testing terminals are connected to each other by a metal wiring layer. Die testing is performed by bringing probes projecting from a probe card into contact with the plurality of die testing terminals.
Claims11
A semiconductor device comprising:
- a semiconductor substrate;
- an input/output terminal array formed on said semiconductor substrate in a two-dimensional array fashion, said input/output terminal array having a plurality of input/output terminals evenly formed on an inner region on said semiconductor substrate;
- a peripheral region formed on said semiconductor substrate, said peripheral region having a plurality of testing terminals equal in number to the number of the input/output terminals;
- a first metal wiring layer for connecting each of said input/output terminals to a dedicated one of said testing terminals located from said input/output terminal;
- and
- input/output circuits arranged along sides of said semiconductor substrate on the peripheral region of said semiconductor substrate, said plurality of testing terminals being respectively arranged between said input/output circuits and the sides of said semiconductor substrate;
- wherein said testing terminals and said input/output terminals are formed of a second metal wiring layer, said input/output terminals are arranged at a place inner to that of said input/output circuits on the semiconductor substrate, and each of said plurality of input/output terminals includes a barrier layer formed over said second metal wiring layer to have a top surface higher than that of each testing terminal, and a bump formed on said barrier layer.
4 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- an input/output terminal array formed on said semiconductor substrate in a two-dimensional array fashion, said input/output terminal array having a plurality of input/output terminals evenly formed on an inner region on said semiconductor substrate;
- a peripheral region formed on said semiconductor substrate, said peripheral region having a plurality of testing terminals equal in number to the number of the input/output terminals;
- and
- a first metal wiring layer for connecting each of said input/output terminals to a dedicated on of said testing terminals located remote from said input/output terminal;
- and
- wherein each of said testing terminals and each of said plurality of input/output terminals are formed of a second metal wiring layer, each of said plurality of input/output terminals has a substantially square distal end, a central line parallel to two opposing sides of the distal end is inclined at about 45° with respect to an arbitrary side of said semiconductor substrate;
- and each of said plurality on input/output terminals includes a barrier layer formed over said second metal wiring layer to have a top surface higher than that of each testing terminal, and a bump formed on said barrier layer.
5 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- an input/output terminal array formed on said semiconductor substrate in a two-dimensional array fashion, said input/output terminal array having a plurality of input/output terminals evenly formed on an inner region on said semiconductor substrate;
- a peripheral region formed on said semiconductor substrate, said peripheral region having a plurality of testing terminals equal in number to the number of the input/output terminals;
- wherein a multilayered wiring structure is formed on said semiconductor substrate;
- wherein said input/output terminals each are constituted by an insulating film, a second metal wiring layer formed on said insulating film, a barrier metal formed on said second metal wiring layer via a conductive anti-etching protection film, and a bump formed on said second metal wiring layer, wherein said barrier metal has a top surface higher than that of each testing terminal;
- wherein each of said testing terminals is constituted by said insulating film and said second wiring layer formed on said insulating film;
- and
- wherein each bump of said input/output terminals is connected to one of said testing terminals via said first wiring layer, said conductive anti-etching protection film and said second wiring layer.
5 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- an input/output terminal array formed on said semiconductor substrate in a two-dimensional array fashion, said input/output terminal array having a plurality of input/output terminals evenly formed on an inner region on said semiconductor substrate;
- a peripheral region formed on said semiconductor substrate, said peripheral region having a plurality of testing terminals equal in a number of the input/output terminals;
- and
- a first metal wiring layer for connecting each of said input/output terminals to a dedicated one of said testing terminals located remote from said input/output terminals;
- wherein said testing terminals and said input/output terminals are formed of a second metal wiring layer connected to said first metal wiring layer, said testing terminals are coated with a conductive anti-etching protection film, and each of said plurality of input/output terminals includes a barrier layer formed over said second metal wiring layer to have a top surface higher than that of each testing terminal, and a bump formed on said barrier layer.
3 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- an input/output terminal array formed on said semiconductor substrate in a two-dimensional array fashion, said input/output terminal array having a plurality of input/output terminals evenly formed on an inner region on said semiconductor substrate;
- a peripheral region formed on said semiconductor substrate;
- said peripheral region having a plurality of testing terminals equal in number to the number of the input/output terminals;
- and
- a first metal wiring layer for connecting each of said input/output terminals to a dedicated one of said testing terminals located remote from said input/output terminals;
- wherein each of said testing terminals and said input/output terminals are formed of an uppermost metal wiring layer of a multilayered wiring structure connected to said first metal wiring layer on said semiconductor substrate, a conductive anti-etching protection film that covers said uppermost metal wiring layer, a barrier metal formed on said anti-etching protection film, and a bump formed on said barrier metal, wherein said barrier metal has a top surface higher than that of each testing terminal.
4 more elements
Dependencies are inferred from the claim text.