Thin film wiring scheme utilizing inter-chip site surface wiring

A thin film layer wiring scheme on a substrate comprising:

• at least two chip connection pads with an inter pad space at a first chip site on a thin film layer:
• a first chip site first directional wiring line interspersed between the first chip site chip connection pads;
• at least one wiring interconnection line connecting one of the first chip site chip connection pads with the first chip site first directional wiring line at the first chip site;
• at least two chip connection pads with another inter pad space at a second chip site on the thin film layer, wherein the at least two chip connection pads at the first chip site are separated from the at least two chip connection pads at the second chip site by a space which is greater than any of said inter pad spaces;
• a second chip site first directional wiring line interspersed between the second chip site chip connection pads;
• wherein there is at least a second chip site second directional wiring line interspersed between the chip connection pads at the second chip site, the second chip site first directional wiring line and second chip site second directional wiring line overlapping but not contacting at the second chip site;
• and
• at least one chip site interconnection line connecting the first chip site first directional wiring line at the first chip site with the second chip site first directional wiring line at the second chip site, wherein the chip connection pads at a first chip site, the chip connection pads at a second chip site, first and second chip site first directional wiring lines, at least one wiring interconnection line and at least one chip site interconnection line all being located on a single sublayer of the thin film layer.

A thin film wiring scheme on a substrate comprising:

• a plurality of chip connection pads at a first chip site with an inter pad spacing on a thin film layer;
• a plurality of directional wiring lines interspersed between the first chip site chip connection pads, at least one of the first chip site directional wiring lines being orthogonal to at least another one of the first chip site directional wiring lines,wherein the orthogonal directional wiring lines at the first chip site overlap but do not contact each other;
• at least one wiring interconnection line connecting one of the first chip site chip connection pads with one of the directional wiring lines at the first chip site;
• a plurality of chip connection pads at a second chip site with another inter pad spacing on the thin film layer, where the first chip site being separated from the second chip site by a space which is greater than any of said inter pad spaces;
• a plurality of directional wiring lines interspersed between the second chip site chip connection pads, at least one of the second chip site directional wiring lines being orthogonal to at least another one of the second chip site directional wiring lines;
• at least one wiring interconnection line connecting one of the second chip site chip connection pads with one of the directional wiring lines at the second chip site;
• and
• a plurality of chip site interconnection lines connecting at least one of the directional wiring lines at the first chip site with at least one of the directional wiring lines at the second chip site, wherein the chip connection pads, directional wiring lines, wiring interconnection lines and chip site interconnection lines all being located on a single sublayer of the thin film layer.

A thin film wiring scheme on a substrate comprising:

• a plurality of chip connection pads at a first chip site with an inter pad spacing on a thin film layer;
• a plurality of directional wiring lines interspersed between the first chip site chip connection pads, at least one of the first chip site directional wiring lines being orthogonal to at least another one of the first chip site directional wiring lines;
• at least one wiring interconnection line connecting one of the first chip site chip connection pads with one of the directional wiring lines at the first chip site;
• a plurality of chip connection pads at a second chip site with another inter pad spacing on the thin film layer, where the first chip site being separated from the second chip site by a space which is greater than any of said inter pad spaces;
• a plurality of directional wiring lines interspersed between the second chip site chip connection pads, at least one of the second chip site directional wiring lines being orthogonal to at least another one of the second chip site directional wiring lines, wherein the orthogonal directional wiring lines at the second chip site overlap but do not contact each other;
• at least one wiring interconnection line connecting one of the second chip site chip connection pads with one of the directional wiring lines at the second chip site;
• and
• a plurality of chip site interconnection lines connecting at least one of the directional wiring lines at the first chip site with at least one of the directional wiring lines at the second chip site, wherein the chip connection pads, directional wiring lines, wiring interconnection lines and chip site interconnection lines all being located on a single sublayer of the thin film layer.