Surface treatment of low-K SiOF to prevent metal interaction

A method for fabricating an integrated circuit, the integrated circuit including a first metal stack, a dielectric layer, and a second metal stack, the dielectric layer being between the first metal stack and the second metal stack, the method comprising:

• providing the first metal stack;
• providing the dielectric layer including a first layer of SiOF and a second layer of SiOF;
• depleting the fluorine from a surface of the layer SiOF with a plasma including NH3, the surface having a first region depleted of fluorine from an edge to a first depth;
• passivating the surface with a plasma including N2O, the surface having a second region extending from the edge to a second depth, the second depth being less than the first depth, the second region being passivated and being disposed within the first region;
• and
• providing the second metal layer.

A method for fabricating an integrated circuit, the integrated circuit including a first metal stack, a dielectric layer, and a second metal stack, the dielectric layer being between the first metal stack and the second metal stack, the method comprising:

• providing the first metal stack;
• providing the dielectric layer including at least one layer including SiOF;
• selectively etching through the top surface to form a via in contact with the first metal stack;
• first depleting fluorine from a top surface of the dielectric layer and from a side surface of the via with the first plasma, the first plasma including NH3;
• first passivating the top surface and the side surface with the second plasma, the second surface including N2O;
• providing a conformal layer of conductive material above the top surface and filling the via with the conductive material;
• removing the conformal layer from the top surface, thereby leaving the conductive material in the via;
• second depleting fluorine from the top surface of the dielectric layer with the first plasma;
• second passivating the top surface with the second plasma;
• and
• providing the second metal.

A method for using low dielectric constant SiOF in a process to manufacture semiconductor integrated circuits, the method comprising the steps of:

• providing the dielectric layer including at least one layer including SiOF;
• selectively etching through the top surface to form a via;
• first depleting fluorine from a top surface of the dielectric layer and from a side surface of the via with the first plasma, the first plasma being ammonia;
• first passivating the top surface and the side surface with the second plasma, the second surface being nitrite;
• providing a conformal layer of conductive material above the top surface and filling the via with the conductive material;
• removing the conformal layer from the top surface, thereby leaving the conductive material in the via;
• second depleting fluorine from the top surface of the dielectric layer with the first plasma;
• and
• second passivating the top surface with the second plasma.

A method of forming metal layers in an integrated circuit, the method comprising:

• providing a first metal stack;
• providing a dielectric layer including fluorine;
• depleting the fluorine from an exposed surface of the dielectric layer with an ammonia treatment, the exposed surface having a first region depleted of fluorine from an edge to a first depth;
• passivating the surface with a plasma, the surface having a second region extending from the edge to a second depth, the second depth being less than the first depth, the second region being passivated and being disposed within the first region;
• providing a second metal stack over the dielectric layer;
• and
• etching a hole in the dielectric layer before the depleting step, wherein an inside surface of the hole is the exposed surface.

A method of forming metal layers in an integrated circuit, the method comprising:

• providing a first metal stack;
• providing a dielectric layer including fluorine;
• depleting the fluorine from a n exposed surface of the dielectric layer with an ammonia treatment;
• passivating the exposed surface after the depleting step, wherein the passivating step utilizes nitrite;
• selectively etching the exposed surface to form a via;
• depleting the fluorine from the side surfaces of the via;
• passivating the side surface of the via utilizing nitrite;
• filling the via with a conductive material;
• and
• providing the second metal stack.