Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher

A method for removing doped silicon dioxide, said method comprising:

• providing a structure including a first portion comprising doped silicon dioxide and a second portion comprising undoped silicon dioxide;
• placing said structure in a chamber of a high density etcher having a upper electrode and a lower electrode;
• and
• exposing said first portion and said second portion to a high density plasma etch process including:
• applying a source power to said upper electrode;
• and
• applying a bias power to said lower electrode, said bias power being in a range from about 200 Watts less than said source power to about 200 Watts greater than said source power, such that a power density less than or equal to about 1000 W source power per 200-mm diameter wafer surface is provided, said doped silicon dioxide being selectively removed at a material removal rate that is at least 10 times greater than the material removal rate of undoped silicon dioxide, said material removal rate of doped silicon dioxide being in a range from about 5,000 Å/min to about 10,000 Å/min.

A method for removing doped silicon dioxide, said process comprising:

• providing a structure including a first portion comprising doped silicon dioxide and a second portion comprising undoped silicon dioxide;
• placing said structure in a high density etcher having a upper electrode and a lower electrode;
• and
• exposing said first portion and said second portion to a high density plasma etch process including:
• introducing an etchant selected from the group consisting of C2F6, CF4, C3F8, C4F10, CH2F2, CHF3, C2HF5, CH3F, and combinations thereof;
• applying a source power to said upper electrode;
• applying a bias power to said lower electrode, said bias power being in a range from about 200 Watts less than said source power to about 200 Watts greater than said source power;
• providing an ion density within said chamber of not less that about 109 ions/cm3;
• and
• providing a source power density less than or equal to about 1000 W per 200-mm diameter wafer surface to a surface of said structure, said doped silicon dioxide being selectively removed at a material removal rate that is at least 10 times greater than the material removal rate of undoped silicon dioxide, said material removal rate of doped silicon dioxide being in a range from about 5,000 Å/min to about 10,000 Å/min.

A process for removing doped silicon dioxide, said process comprising:

• forming a first layer on a substrate, said first layer comprising doped silicon dioxide;
• forming a second layer on said first layer, said second layer comprising undoped silicon dioxide;
• forming an opening through said second layer to expose a surface on said first layer;
• and
• conducting a high density plasma etch on said first layer and on said second layer in a high density plasma etcher having a lower electrode by applying:
• a bias power to the lower electrode;
• and
• a source power density to both of said first layer and said second layer in an amount less than or equal to about 1000 W per 200-mm diameter wafer surface, wherein said bias power is in a range from about 200 Watts less than said source power density to about 200 Watts greater than said source power density, thereby selectively removing doped silicon dioxide from said first layer through said opening at a material removal rate that is greater than the material removal rate of undoped silicon dioxide from said second layer.

A process for forming a contact to a semiconductor substrate, said process comprising:

• forming a first layer on a semiconductor substrate, said first layer comprising doped silicon dioxide;
• forming a second layer, the second layer being patterned and on said first layer, said second layer comprising undoped silicon dioxide, and wherein a portion of said first layer under said pattern is exposed;
• conducting a high density plasma etch on said first layer and on said second layer in a high density plasma etcher having a lower electrode by applying:
• a bias power to the lower electrode;
• and
• a source power density to said first layer and said second layer in an amount less than or equal to about 1000 W per 200-mm diameter wafer surface, wherein the bias power is in a range from about 200 Watts less than said source power density to about 200 Watts greater than said source power density, thereby selectively removing doped silicon dioxide from said first layer through said pattern to form an opening in said first layer, said opening being defined by an exposed contact surface on said semiconductor substrate and a sidewall substantially orthogonal to said exposed contact surface, said doped silicon dioxide being selectively removed from said first layer at a material removal rate that is greater than the material removal rate of undoped silicon dioxide from said second layer;
• and
• forming a contact plug comprising a conductive material on said exposed surface within said opening.

A process for removing doped silicon dioxide, said process comprising:

• providing a multilayer structure having:
• a first layer on a substrate, said first layer comprising doped silicon dioxide;
• and
• a second layer on said first layer, said second layer being comprising undoped silicon dioxide,
• forming a primary opening and a secondary opening in said second layer, said primary opening and said secondary opening extending to said first layer;
• forming a photoresist layer over said second layer, said photoresist layer at least partially filling said secondary opening and substantially not filling said primary opening;
• conducting a high density plasma etch on said first layer and on said second layer through said primary opening in a high density plasma etcher having a lower electrode by applying:
• a bias power to the lower electrode;
• and
• a source power density to said first layer and to said second layer in an amount less than or equal to about 1000 W per 200-mm diameter wafer surface, wherein:
• the bias power is in a range from about 200 Watts less than said source power density to about 200 Watts greater than said source power density;
• said doped silicon dioxide is selectively removed from said first layer through said primary opening at a material removal rate that is:
• at least 10 times greater than the material removal rate of undoped silicon dioxide from said second layer;
• and
• greater than the material removal rate of photoresist material from said photoresist layer.

A process for removing doped silicon dioxide, said process comprising:

• forming a silicon dioxide-containing layer over a first series of gate stacks on a substrate;
• forming a second series of gate stacks on said silicon dioxide-containing layer, said second series defining at least one space between any two adjacent gate stacks of said second series, each said gate stack of said second series including:
• an undoped silicon dioxide-containing layer which defines an upper surface on each said gate stack of said second series;
• and
• a spacer in contact with said undoped silicon dioxide-containing layer, said spacer defining a lateral surface on each said gate stack of said second series;
• and
• conducting a high density plasma etch on said silicon dioxide-containing layer and on said undoped silicon dioxide-containing layer in a high density plasma etcher having a lower electrode by applying:
• a bias power to the lower electrode;
• and
• a source power density to said silicon dioxide-containing layer and to said undoped silicon dioxide-containing layer in an amount less than or equal to about 1000 W per 200-mm diameter wafer surface, said bias power being applied in a range from about 200 Watts less than said source power to about 200 Watts greater than said source power, thereby selectively removing at least silicon dioxide from said silicon dioxide-containing layer through said at least one space at a material removal rate that is greater than the material removal rate of undoped silicon dioxide from said undoped silicon dioxide-containing layer.

A process for removing doped silicon dioxide, said process comprising:

• forming a second layer over a semiconductor substrate, said second layer comprising undoped silicon dioxide;
• forming a first layer over said second layer, said first layer comprising doped silicon dioxide;
• and
• conducting a high density plasma etch on said first layer and on said second layer in a high density plasma etcher having a lower electrode by applying:
• a bias power to the lower electrode;
• and
• a source power density being applied to said first layer and to said second layer in an amount less than or equal to about 1000 W per 200-mm diameter wafer surface, said bias power being applied in a range from about 200 Watts less than said source power to about 200 Watts greater than said source power, said doped silicon dioxide being selectively removed from said first layer to expose a portion of said second layer, said doped silicon dioxide being removed at a material removal rate greater than the material removal rate of undoped silicon dioxide from said second layer.

A process for forming a contact opening, said process comprising:

• providing a gate oxide layer over a semiconductor substrate comprising a semiconductor material;
• providing a pair of gate stacks in spaced relation to one another on said gate oxide layer, each of said gate stacks having at least one conductive layer formed therein and an undoped silicon dioxide layer extending over said conductive layer, a contact surface on said semiconductor substrate being positioned between said pair of gate stacks;
• forming a spacer comprising a spacer material adjacent to each of said gate stacks;
• forming a doped silicon dioxide layer over said pair of gate stacks and over said contact surface;
• and
• high-density-plasma etching in a high density plasma etcher having a lower electrode, wherein:
• a bias power is applied to the lower electrode;
• a source power density is applied to said doped silicon dioxide layer and to at least one of said undoped silicon dioxide layer in an amount less than or equal to about 1000 W per 200-mm diameter wafer surface;
• the bias power is in a range from about 200 Watts less than said source power density to about 200 Watts greater than said source power density;
• doped silicon dioxide is selectively removed from said doped silicon dioxide layer to form a contact opening extending to said contact surface;
• said doped silicon dioxide is removed at a material removal rate that is at least 10 times greater than the material removal rates for each of:
• undoped silicon dioxide from said undoped silicon dioxide layer;
• said spacer material from said spacer;
• and
• said semiconductive material from said semiconductor substrate.

A process for forming a gate structure, said process comprising:

• providing a multilayer structure over a semiconductor substrate;
• depositing an undoped silicon dioxide layer over said multilayer structure using a precursor having a gaseous silane, hydrogen, and oxygen flow;
• forming a patterned first photoresist layer over said undoped silicon dioxide layer, said patterned first photoresist layer having a first selected pattern;
• etching said undoped silicon dioxide layer and said multilayer structure through said first selected pattern to expose a contact surface on said semiconductor substrate;
• removing said first photoresist layer;
• depositing a layer of a nonconductive material over both of said undoped silicon dioxide layer and said contact surface;
• etching said layer of said nonconductive material to form a spacer over a lateral side of said undoped silicon dioxide layer and over a lateral side of said multilayer structure, said spacer being generally perpendicular to said semiconductor substrate;
• depositing a doped silicon dioxide layer over both of said multilayer structure and said undoped silicon dioxide layer;
• forming a patterned second photoresist layer over said doped silicon dioxide layer, said patterned second photoresist layer having a second selected pattern;
• conducting a high density plasma etch, wherein:
• said high density plasma etch is conducted in a high density plasma etcher having a lower electrode to which a bias power is applied;
• a source power density is applied to said doped silicon dioxide layer and to said undoped silicon dioxide layer in an amount less than or equal to about 1000 W per 200-mm diameter wafer surface;
• the bias power is in a range from about 200 Watts less than said source power density to about 200 Watts greater than said source power density;
• doped silicon dioxide is selectively removed from said doped silicon dioxide layer through said second selected pattern to expose said contact surface;
• said doped silicon dioxide is removed at a material removal rate that is at least 10 times greater than:
• the material removal rates for each of:
• undoped silicon dioxide from said undoped silicon dioxide layer;
• nonconductive material from said spacer;
• semiconductive material from said semiconductor substrate;
• and
• photoresist material from photoresist layer;
• removing said second photoresist layer;
• and
• forming a contact plug that comprises a conductive material in contact with said contact surface.

A process for forming a gate structure, comprising:

• providing a multilayer structure over a semiconductor substrate, said multilayer structure comprising successive layers of gate oxide, polysilicon, and refractory metal silicide;
• depositing an undoped silicon dioxide layer over said multilayer structure using a precursor having a gaseous silane, hydrogen, and oxygen flow;
• forming a patterned first photoresist layer over said undoped silicon dioxide layer, the patterned first photoresist layer having a first selected pattern;
• etching said undoped silicon dioxide layer and said multilayer structure through said first selected pattern to expose a contact surface on said semiconductor substrate;
• removing said first photoresist layer;
• forming a layer of a nonconductive material over both of said undoped silicon dioxide layer and said contact surface;
• etching said layer of said nonconductive material to form a spacer over a lateral side of said undoped silicon dioxide layer and over a lateral side of said multilayer structure, said spacer being generally perpendicular to said semiconductor substrate;
• forming a doped silicon dioxide layer over said multilayer structure and over said contact surface;
• forming a patterned second photoresist layer over said doped silicon dioxide layer, said patterned second photoresist layer having a second selected pattern;
• conducting a high density plasma etch wherein:
• said high density plasma etch is conducted in a high density plasma etcher having a lower electrode to which a bias power is applied;
• a source power density is applied to said doped silicon dioxide layer and to said undoped silicon dioxide layer in an amount less than or equal to about 1000 W per 200-mm diameter wafer surface;
• the bias power is in a range from about 200 Watts less than said source power density to about 200 Watts greater than said source power density;
• doped silicon dioxide is selectively removed from said doped silicon dioxide layer through said second selected pattern to expose said contact surface;
• said doped silicon dioxide is removed at a material removal rate that is at least 10 times greater than:
• the material removal rate for each of:
• undoped silicon dioxide from said undoped silicon dioxide layer;
• nonconductive material from said spacer;
• semiconductive material from said semiconductor substrate;
• and
• photoresist material from said second photoresist layer;
• removing said second photoresist layer;
• and
• forming a contact plug comprising a conductive material in contact with said contact surface.

A method of forming a self-aligned contact opening, said method comprising:

• providing a pair of gate stacks in spaced relation to one another on a semiconductor substrate, each of said gate stacks being covered by an undoped silicon dioxide layer;
• forming a spacer adjacent to each of said gate stacks;
• forming a doped silicon dioxide layer over said pair of gate stacks and over said semiconductor substrate;
• forming a patterned photoresist layer over said doped silicon dioxide layer;
• and
• conducting a high density plasma etch in a high density plasma etcher having a lower electrode, wherein:
• a bias power is applied to the lower electrode;
• a source power density is applied to said doped silicon dioxide layer and to at least one said undoped silicon dioxide layer in an amount less than or equal to about 1000 W per 200-mm diameter wafer surface;
• the bias power is in a range from about 200 Watts less than said source power density to about 200 Watts greater than said source power density;
• doped silicon dioxide is selectively removed from said doped silicon dioxide layer between said pair of gate stacks and through said pattern to form a self-aligned contact opening extending to said contact surface;
• doped silicon dioxide is removed at a substantially greater material removal rate than that of undoped silicon dioxide from said undoped silicon dioxide layer;
• and
• said undoped silicon layer resists said high density plasma etch.