Method for forming a bitline contact via within a memory cell structure

A method for fabricating a memory cell structure comprising:

• providing a semiconductor substrate;
• forming within and upon the semiconductor substrate a pair of field effect transistor (FET) devices comprising a series of three source/drain regions formed into the semiconductor substrate and separated by a pair of gate electrodes formed over the semiconductor substrate;
• forming over the pair of field effect transistor (FET) devices, and electrically connected with two of the series of three source/drain regions, a pair of capacitor structures defining a contact aperture having at its bottom a contact region for a third of the series of three source/drain regions;
• forming upon the pair of capacitor structures and within the contact aperture a blanket conformal isolation layer having an upper region formed upon the pair of capacitor structures and a lower region formed interposed between the pair of capacitor structures;
• forming upon the blanket conformal isolation layer a blanket variable thickness masking layer having a greater thickness over the upper region of the blanket conformal isolation layer than over the lower region of the blanket conformal isolation layer;
• etching completely through the blanket variable thickness masking layer and the blanket conformal isolation layer at the lower region of the blanket conformal isolation layer but not the upper region of the blanket conformal isolation layer to form a pair of patterned conformal isolation layers and a pair of patterned variable thickness masking layers which define a contact via exposing the contact region for the third of the series of three source/drain regions.

A method for fabricating a memory cell structure comprising:

• providing a semiconductor substrate;
• forming within and upon the semiconductor substrate a pair of field effect transistor (FET) devices comprising a series of three source/drain regions formed into the semiconductor substrate and separated by a pair of gate electrodes formed over the semiconductor substrate;
• forming over the pair of field effect transistor (FET) devices, and electrically connected with two of the series of three source/drain regions, a pair of capacitor structures defining a contact aperture having at its bottom a contact region for a third of the series of three source/drain regions;
• forming upon the pair of capacitor structures and within the contact aperture a blanket conformal isolation layer having an upper region formed upon the pair of capacitor structures and a lower region formed interposed between the pair of capacitor structures;
• forming upon the blanket conformal isolation layer a blanket variable thickness dielectric masking layer having a greater thickness over the upper region of the blanket conformal isolation layer than over the lower region of the blanket conformal isolation layer;
• etching completely through the blanket variable thickness dielectric masking layer and the blanket conformal isolation layer at the lower region of the blanket conformal isolation layer but not the upper region of the blanket conformal isolation layer to form a pair of patterned conformal isolation layers and a pair of patterned variable thickness dielectric masking layers which define a contact via exposing the contact region for the third of the series of three source/drain regions.

A method for fabricating a memory cell structure comprising:

• providing a semiconductor substrate;
• forming within and upon the semiconductor substrate a pair of field effect transistor (FET) devices comprising a series of three source/drain regions formed into the semiconductor substrate and separated by a pair of gate electrodes formed over the semiconductor substrate;
• forming over the pair of field effect transistor (FET) devices, and electrically connected with two of the series of three source/drain regions, a pair of capacitor structures defining a contact aperture having at its bottom a contact region for a third of the series of three source/drain regions;
• forming upon the pair of capacitor structures and within the contact aperture a blanket conformal isolation layer having an upper region formed upon the pair of capacitor structures and a lower region formed interposed between the pair of capacitor structures;
• forming upon the blanket conformal isolation layer a blanket variable thickness conductor masking layer having a greater thickness over the upper region of the blanket conformal isolation layer than over the lower region of the blanket conformal isolation layer;
• etching completely through the blanket variable thickness conductor masking layer and the blanket conformal isolation layer at the lower region of the blanket conformal isolation layer but not the upper region of the blanket conformal isolation layer to form a pair of patterned conformal isolation layers and a pair of patterned variable thickness conductor masking layers which define a contact via exposing the contact region for the third of the series of three source/drain regions.