US 6,444,554 B1Granted

Method of making a non-volatile memory and semiconductor device

AssigneeHitachi, Ltd.

InventorsTetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine

Life of this patent

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Abstract

A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Claims9

Dependent claims

A method of manufacturing a semiconductor device, comprising steps of:

(a) forming a first conductive film over a memory cell forming region and a peripheral circuit region of a semiconductor substrate;
(b) patterning said first conductive film in said memory cell forming region to form a first conductor pattern;
(c) forming an insulating film over said first conductor pattern, said memory cell forming region and said first conductive film of said peripheral circuit region and polishing said insulating film to form a first insulating film on non-patterned portions of said first conductor pattern;
(d) forming a second conductor pattern over said first conductor pattern, said first insulating film and said first conductive film of said peripheral circuit region;
(e) forming a second insulating film over said second conductor pattern;
(f) forming a second conductive film over said second insulating film;
and
(g) patterning said second conductive film, said second conductor pattern, said first conductor pattern and said first conductive film of said peripheral circuit region at said memory cell forming region and said peripheral circuit region,
wherein, in said step (g), said second conductive film of said memory cell forming region is patterned to form a control gate electrode of a memory cell,
wherein, in said step (g), said first conductor pattern and said second conductor pattern of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and
wherein, in said step (g), at least said first conductive film and said second conductor pattern of said peripheral circuit region are patterned to form a gate electrode of a MISFET.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/011,731Filed 11 Dec 2001 · continuation
Priority: JP 9-7717528 Mar 1997
Published: US 2002/0064898 A130 May 2002
Granted: 3 Sep 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10B 41/49
Simultaneous manufacture of periphery and memory cells: comprising different types of peripheral transistor
G11C 16/0466
Using variable threshold transistors, e.g. FAMOS: comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon…
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout