Method of fabricating a semiconductor device
AssigneesMitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
InventorsHiroshi Matsuo, Yuichi Yokoyama, Takuji Oda, Kiyoshi Maeda, Shinya Inoue, Yuji Yamamoto
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Abstract
A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO2 layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.
Claims5
A method of fabricating a semiconductor device, comprising the steps of:
- forming a gate electrode on a main surface of a semiconductor substrate;
- forming a hard mask insulating layer greater than about 120 nm thick on a top surface of said gate electrode;
- forming a thin insulating layer to cover said gate electrode and said hard mask insulating layer;
- forming a nitride stopper layer between about 40 nm and 100 nm thick directly on said thin insulating layer;
- forming an interlayer insulating layer to cover said nitride stopper layer;
- forming a contact hole that reaches said main surface and forming a sidewall nitride layer on a side surface of said gate electrode by etching said interlayer insulating layer, said nitride stopper layer, and said thin insulating layer successively, said sidewall nitride layer to have a height in a direction perpendicular to said main surface greater than a thickness of said gate electrode in said direction perpendicular to said main surface by at least 20 nm;
- and
- forming an interconnection layer in said contact hole.
A method of fabricating a semiconductor device, comprising the steps of:
- forming a gate electrode on a main surface of a semiconductor substrate;
- forming a hard mask insulating layer on a top surface of said gate electrode;
- forming a thin insulating layer to cover said gate electrode and said hard mask insulating layer;
- forming a nitride stopper layer directly on said thin insulating layer;
- forming an interlayer insulating layer to cover said nitride stopper layer;
- forming a contact hole that reaches said main surface and forming a sidewall nitride layer on a side surface of said gate electrode by etching said interlayer insulating layer, said nitride stopper layer, and said thin insulating layer successively;
- forming an interconnection layer in said contact hole, wherein
- said step of forming said contact hole includes a step of forming a concave portion by isotropically etching said main surface which is exposed, and
- said step of forming said interconnection layer includes a step of forming said interconnection layer to fill said concave portion.
A method of fabricating a semiconductor device having a memory cell portion and a peripheral circuit portion, comprising the steps of:
- forming a first hard mask insulating layer on a main surface of a semiconductor substrate located in said memory cell portion with a first gate electrode interposed, and forming a second hard mask insulating layer on said main surface located in said peripheral circuit portion with a second gate electrode interposed;
- forming a thin insulating layer to cover said first and second hard mask insulating layers and side surfaces of said first and second gate electrodes;
- forming a nitride stopper layer directly on said thin insulating layer;
- forming a first mask layer to cover said nitride stopper layer located in said memory cell portion;
- exposing said second hard mask insulating layer and forming a pair of sidewall nitride layers that covers a side surface of said second gate electrode by etching said nitride stopper layer using said first mask layer;
- forming an interlayer insulating layer to cover said nitride stopper layer and said second hard mask insulating layer;
- forming a second mask layer on said interlayer insulating layer;
- forming a first contact hole that selectively exposes said main surface by etching said interlayer insulating layer, said nitride stopper layer and said thin insulating layer located in said memory cell portion successively, and forming a second contact hole that reaches said second gate electrode by etching said interlayer insulating layer and said second hard mask insulating layer located in said peripheral circuit portion successively, using said second mask layer;
- and
- forming first and second interconnection layers respectively in said first and second contact holes.
Dependencies are inferred from the claim text.