Dicing tape and a method of dicing a semiconductor wafer
AssigneeLintec Corporation
InventorsHideo Senoo, Takeshi Kondo
Life of this patent
Estimating the term…
Loading patent…
AssigneeLintec Corporation
InventorsHideo Senoo, Takeshi Kondo
Estimating the term…
A dicing tape comprising a substrate sheet and a pressure-sensitive adhesive layer formed on one surface of the substrate sheet, wherein the substrate sheet comprises an upper layer in direct contact with the pressure-sensitive adhesive layer, an intermediate layer adjacent to the upper layer, and a lower layer adjacent to the intermediate layer, and an anti-extensibility (A) of the upper layer, an anti-extensibility (B) of the intermediate layer, and an anti-extensibility (C) of the lower layer satisfy the equation (I): B<A≦C (I), the anti-extensibility being a product of a modulus of elasticity and a layer thickness, is disclosed. The present dicing tape can uniformly and sufficiently enlarge dicing lines without affect by a modulus of elasticity of a pressure-sensitive adhesive, and is rarely broken at the dicing lines.
A dicing tape comprising a substrate sheet and a pressure-sensitive adhesive layer formed on one surface of said substrate sheet, wherein said substrate sheet comprises an upper layer in direct contact with said pressure-sensitive adhesive layer, an intermediate layer adjacent to said upper layer, and a lower layer adjacent to said intermediate layer, and an anti-extensibility (A) of said upper layer, an anti-extensibility (B) of said intermediate layer, and an anti-extensibility (C) of said lower layer satisfying the equation (I):
A dicing tape comprising a substrate sheet and a pressure-sensitive adhesive layer formed on one surface of said substrate sheet, wherein said substrate sheet comprises an upper layer in direct contact with said pressure-sensitive adhesive layer, an intermediate layer adjacent to said upper layer, and a lower layer adjacent to said intermediate layer, and an anti-extensibility (A) of said upper layer, an anti-extensibility (B) of said intermediate layer, and an anti-extensibility (C) of said lower layer satisfying the equation (I):
A method of dicing a semiconductor wafer into individual chips which comprises:
Dependencies are inferred from the claim text.