Polishing apparatus and method for forming an integrated circuit

A method for forming an integrated circuit comprising the steps of:

• providing a substrate having a center and a perimeter;
• forming a layer of material overlying the substrate;
• providing a polishing pad having a perimeter and a center, the polishing pad comprising a first polishing region, a second polishing region, and a third polishing region, wherein the second polishing region lies between the first polishing region and the third polishing region;
• using an alignment detector to align the substrate to the second polishing region of the polishing pad, such that the center of the substrate overlies the second polishing region, a first portion of the perimeter of the substrate overlies the first polishing region, and a second portion of the perimeter of the substrate overlies the third polishing region;
• and
• polishing the layer of material overlying the substrate using the polishing pad, wherein the center of the substrate remains at a fixed distance from the perimeter of the polishing pad while the layer of the material is polished, wherein the first polishing region comprises a first plurality of holes having a first hole depth and a first hole width, the second polishing region comprises a second plurality of holes having a second hole depth and a second hole width, and the third polishing region comprises a third plurality of holes having a third hole depth and a third hole width, wherein the second hole width is different than the first hole width and the third hole width.