Computer system, and video decoder used in the system
AssigneeKabushiki Kaisha Toshiba
InventorYasuhiro Ishibashi
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AssigneeKabushiki Kaisha Toshiba
InventorYasuhiro Ishibashi
Estimating the term…
A VGA controller has a simple field synthesis mode and an interpolation mode, both for interlace/noninterlace conversion. The switching between these two modes is dynamically controlled in accordance with the value of a progressive flag signal output from a DVD decoder 112. If the value of the progressive flag is “1”, this means that frame data is being decoded, so that the simple field synthesis mode is used. On the other hand, if the value of the progressive flag is “0”, this means that the decoding of field data has been started, so that the conversion mode is switched to the interpolation mode. In the interpolation mode, fields are not synthesized together, and a line which is absent in each field is interpolated so as to produce frames for noninterlace display. The mask circuit of the DVD decoder receives a repeat first field flag register (Rep-Reg), each time signal Vsync is output. If the repeat first field flag is “1”, signals Vsync and Hsync corresponding to the next field are masked. The signals are automatically released from the masked state when signal Vsync is output next. During the period in which signals Vsync and Hsync are masked, the VGA controller does not capture video data. Accordingly, repeat fields can be easily excluded from the field synthesis processing.
A display control device comprising:
A display control device comprising:
A display control device comprising:
A method for displaying an image, the method comprising:
A method for displaying an image, the method comprising:
A method for displaying an image, the method comprising:
Dependencies are inferred from the claim text.