Receiver for pseudo-noise signals from a satellite radio-navigation systems

A receiver of pseudonoise signals of satellite radio navigation systems comprising:

• an antenna;
• a radio-frequency converter connected in series with the antenna;
• an N-channel digital correlator connected to the radio frequency converter;
• and
• a processor connected to the N-channel digital correlator,
• wherein:
• the antenna is adapted to receive signals of satellite radio navigation systems GPS and GLONASS,
• the radio-frequency converter comprises:
• an input unit connected to the antenna and including at least one band-pass filter connected to the output of the input unit,
• a first unit which performs first conversion of frequency of the signals of the satellite radio navigation systems GPS and GLONASS, the unit comprising at least a first amplifier and a first mixer connected to the output of the unit for first conversion of frequency of signals,
• a first channel and a second channel which perform second conversion of the frequency of signals of the satellite radio navigation systems GPS and GLONASS, respectively, the first channel comprises a first filter and a second mixer connected in series, and the second channel comprises a second filter and a third mixer connected in series,
• a second unit which generates a signal of a first heterodyne frequency,
• a third unit which generates a signal of clock frequency and a signal of a second heterodyne frequency,
• wherein an output of the signal of the first heterodyne frequency is connected to a reference input of the first mixer of the first unit, an output of the signal of the second heterodyne frequency is connected to a reference input of the second mixer and to a reference input of the third mixer, and outputs of the first and second channels and an output of the signal of the clock frequency form a first signal output, a second signal output and a clock output of the radio-frequency converter;
• the N-channel digital correlator comprises:
• a first signal input, a second signal input and a clock input respectively connected to the first signal output, the second signal output and the clock output of the radio frequency converter, and
• N channels, each of the N channels comprising:
• an input signal switch having first and second inputs connected to the first and second signal inputs of the N-channel digital correlator,
• a data exchange unit,
• first, second, third, fourth, fifth and sixth storage units,
• first, second, third, fourth, fifth and sixth correlators,
• a digital carrier generator,
• a control register,
• a digital code generator,
• digital mixers of in-phase and quadrature correlation processing channels,
• a reference C/A code generator,
• a programmable delay line,
• an in-phase and a quadrature correlation processing channels,
• a shaper of delayed strobes,
• a key, and
• an adder,
• wherein
• the data exchange unit is connected through respective data buses to the processor, to outputs of the first, second, third and fourth storage units, to a control input of the digital carrier generator, to a control input of the control register, to a control input of the digital code generator and to a first input of the reference C/A code generator,
• clock inputs of the first, second, third and fourth storage units, the digital code generator, the digital carrier generator and the programmable delay line are connected to the clock input of the N-channel digital correlator,
• an output of the input signal switch is connected to first inputs of the digital mixers of the in-phase and quadrature correlation processing channels,
• second inputs of the digital mixers of the inphase and quadrature correlation processing channels are connected to “cosine” and “sine” outputs of the digital carrier generator, respectively,
• outputs of the digital mixers of the in-phase and quadrature correlation processing channels are connected to a junction between interconnected first inputs of the first and second correlators and to a junction between interconnected first inputs of the third and fourth correlators,
• outputs of the first, second, third, and fourth correlators are connected, respectively, to signal inputs of the first, second, third and fourth storage units,
• second inputs of the first and fourth correlators are connected to an output of a punctual P copy of a reference C/A code of the programmable delay line,
• first input of the programmable delay line is connected to an output of the reference C/A code generator,
• a second input of the reference C/A code generator is connected to an output of the digital code generator,
• a second input of the programmable delay line and a third input of the reference C/A code generator are connected, respectively, to a first and second outputs of the control register,
• a third output of the control register is connected to a third input of the input signal switch;
• an output of the second mixer is connected to the output of the first channel through a controlled-gain amplifier and a threshold device made in a form of a two-bit level-controlled quantizer connected in series;
• an output of the second unit is connected to a first frequency divider and a second frequency divider which divide the output of the second unit by eight;
• outputs of the first and second frequency dividers form, respectively, the signal of the second heterodyne frequency and the signal of the clock frequency;
• outputs of the fifth and the sixth storage units are connected through respective data buses to the data exchange unit, and clock inputs of the fifth and the sixth storage units are connected to the clock input of the N-channel digital correlator;
• outputs of the fifth and sixth correlators are connected, respectively, to signal inputs of the fifth and sixth storage units;
• a first input of the adder is connected to an output of a difference E−L between an early E and a late L copy, or the early E copy of the reference C/A code of the programmable delay line;
• a second input of the adder is connected to an output of the key, and an output of the adder is connected to second inputs of the second and third correlators;
• first inputs of the fifth and sixth correlators are connected, respectively, to the outputs of the digital mixers of the in-phase and quadrature correlation processing channels,
• the output of the shaper of delayed strobes is connected to second inputs of the fifth and sixth correlators and to signal input of the key,
• a control input of the key is connected to a fourth output of the control register;
• a first input of the shaper of delayed strobes is connected to the output of the punctual P copy of the reference C/A code of the programmable delay line,
• and a second input of the shaper of delayed strobes is connected to an output of the digital code generator.