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US 6,441,769 B1Granted
Overcoming finite amplifier gain in a pipelined analog to digital converter
AssigneeTexas Instruments Incorporated
InventorKrishnaswamy Nagaraj
Life of this patent
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Abstract
An apparatus for correcting for the finite gain of an amplifier assembly in a pipelined analog to digital converter (ADC) is disclosed in which an input signal to an amplifier module of one stage of the pipelined ADC is sampled and provided to the input of an amplifier of a subsequent stage as a feed-forward error correction signal. The feed-forward correction signal is subtracted in the next stage from the output residue signal of the previous stage input to the second subsequent stage amplifier in order to remove part of the output signal from the first stage that includes the finite gain of the amplifier.
Claims19
A pipelined analog-to-digital converter comprising:
- a plurality of stages, each stage having a stage input and a stage output, the stage input receiving a stage input signal and the output providing a residue output signal;
- each stage including:
- an analog-to-digital converter having an input and an output, the input coupled to the stage input and the analog-to-digital converter configured and arranged to provide as an output an N-bit digital output signal representative of the input signal;
- a digital-to-analog converter having an input and an output, the input sampling the N-bit to digital output signal, the digital-to-analog converter configured and arranged to provide as an output an analog output signal representative of the digital output signal;
- a subtraction module configured and arranged to subtract the analog output signal from the input signal and to provide a subtracted analog signal;
- an amplifier assembly having a gain factor of 2N, the amplifier assembly having an input coupled to the subtracted analog signal, and the amplifier assembly configured and arranged to provide as an output signal the residue output signal output of the stage that is equal to the amplified subtracted analog signal;
- a sampling network including a sampled signal input coupled to the input of the amplifier assembly, and an output, and the sampling network configured and arranged to provide a feed-forward error correction signal that is the negative of the sampled signal to the subtraction module of a subsequent stage.
4 more elements
A pipelined analog-to-digital converter comprising:
- a plurality of stages, each stage having a stage input and a stage output, the initial stage of the plurality of stages coupled to an input signal, wherein each subsequent stage receives the stage output residue signal of the previous stage as a stage input signal, each stage including an amplifier circuit that provides the stage output residue signal, the amplifier circuit including a plurality of electronic components and a N-bit analog-to-digital converter providing an N-bit output for the particular stage;
- a compensation module of the first stage coupled to the input of the amplifier circuit and coupled the second stage subsequent to said first stage, wherein the feed-forward compensation module of the first stage provides a feed-forward compensation signal to the second stage to remove the stage output residue signal portions of the stage output residue signal contributed by the non-ideal operation of the plurality of electronic components of the amplifier circuit that provides the stage output residue signal in the first stage.
A pipelined analog-to-digital converter comprising:
- a plurality of stages, each stage having a stage input and a stage output, the initial stage of the plurality of stages coupled to an input signal, wherein each subsequent stage receives the stage output residue signal of the previous stage as a stage input signal, each stage including an amplifier circuit that provides the stage output residue signal, the amplifier circuit including a plurality of electronic components and a N-bit analog-to-digital converter providing an N-bit output for the particular stage;
- a compensation module of the first stage coupled to the input of the amplifier circuit and wherein the input to the first input of the operational amplifier is sampled, a processor coupled to the sampled input of the first operational amplifier wherein the processor computes the gain of the operational amplifier, a calibration memory coupled to the processor and stores a plurality of correction factors each corresponding to at least one of a plurality of gain values, wherein the memory retrieves a correction factor based on the input gain value, a calibration circuit coupled to memory to receive the correction factor, and the calibration circuit further coupled to the N-bit digital output of the first stage, and configured and arranged to provide a digital correction value that is subtracted from the N-bit digital output of the particular stage, wherein the digital correction value of removes the error in the N-bit digital output that is contributed by the non-ideal operation of the plurality of electronic components of the amplifier circuit in the first stage.
Dependencies are inferred from the claim text.