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US 6,441,765 B1Granted
Analog to digital converter with enhanced differential non-linearity
AssigneeMarvell International Ltd.
InventorFarbod Aram
Life of this patent
Estimating the term…
Abstract
A bit-and-one-half analog to digital converter comprising a multiplying analog to digital converter (MDAC) operating in cooperation with a comparator which generates a two-bit digital output signal by comparison of an output of the MDAC against a pair of thresholds, wherein the thresholds are stretched outwardly from symmetrical thresholds centered at +/−¼ of the comparison range.
Claims41
A bit-and-one-half analog to digital converter comprising a multiplying analog to digital converter operating in cooperation with a comparator which generates a digital output signal by comparison of an output of said multiplying analog to digital converter against a pair of thresholds, wherein said thresholds are stretched outwardly from symmetrical thresholds centered at +/−¼ of the comparison range.
A bit-and-one-half analog to digital converter comprising:
- a switched capacitive sample and amplification circuit that accepts an analog input voltage and generates a multiplied analog output voltage;
- and
- a comparator which generates a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit;
- wherein said switched capacitive sample and amplification circuit samples the analog input voltage during a first sampling phase in which the voltage is stored on a pair of switched capacitors, and generates the amplified analog output voltage during a second amplification phase in which one of the capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator and in which the other capacitor is biased with a reference voltage also selected in dependence on the digital output;
- and
- wherein said comparator generates the digital output by comparison of the generated analog output voltage against a pair of thresholds, said thresholds being stretched outwardly from symmetrical thresholds centered at +/−¼ of the comparison range.
3 more elements
A multi-stage pipelined analog to digital converter comprising:
- plural stages arranged in series relative to each other, each stage accepting an input analog voltage and generating a residual analog voltage together with a digital output;
- and
- a correction circuit for accepting the digital output from each of said plural stages and for generating a digital output in correspondence to an analog input voltage;
- wherein each stage comprises a switched capacitive sample and amplification circuit that accepts an analog input voltage and generates a multiplied analog output voltage and a comparator which generates a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit;
- wherein said switched capacitive sample and amplification circuit samples the analog input voltage during a first sampling phase in which the voltage is stored on a pair of switched capacitors, and generates the amplified analog output voltage during a second amplification phase in which one of the capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator and in which the other capacitor is biased with a reference voltage also selected in dependence on the digital output;
- and
- wherein said comparator generates the digital output by comparison of the generated analog output voltage against a pair of thresholds, said thresholds being stretched outwardly from symmetrical thresholds centered at +/−¼ of the comparison range.
4 more elements
A bit-and-one-half analog to digital converter comprising multiplying analog to digital converter (multiplying analog to digital converter ) means for operating in cooperation with comparator means for generating a digital output signal by comparison of an output of said multiplying analog to digital converter means against a pair of thresholds, wherein said thresholds are stretched outwardly from symmetrical thresholds centered at +/−¼ of the comparison range.
A bit-and-one-half analog to digital converter comprising:
- switched capacitive sample and amplification circuit means for accepting an analog input voltage and for generating a multiplied analog output voltage;
- and
- comparator means for generating a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit means;
- wherein said switched capacitive sample and amplification circuit means samples the analog input voltage during a first sampling phase in which the voltage is stored on a pair of switched capacitors, and generates the amplified analog output voltage during a second amplification phase in which one of the capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator means and in which the other capacitor is biased with a reference voltage also selected in dependence on the digital output;
- and
- wherein said comparator means generates the digital output by comparison of the generated analog output voltage against a pair of thresholds, said thresholds being stretched outwardly from symmetrical thresholds centered at +/−¼ of the comparison range.
3 more elements
A multi-stage pipelined analog to digital converter comprising;
- plural stage means arranged in series relative to each other, each stage means for accepting an input analog voltage and for generating a residual analog voltage together with a digital output;
- and
- correction circuit means for accepting the digital output from each of said plural stage means and for generating a digital output in correspondence to an analog input voltage;
- wherein each stage means comprises a switched capacitive sample and amplification circuit means for accepting an analog input voltage and for generating a multiplied analog output voltage and a comparator means for generating a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit means;
- wherein said switched capacitive sample and amplification circuit means samples the analog input voltage during a first sampling phase in which the voltage is stored on a pair of switched capacitors, and generates the amplified analog output voltage during a second amplification phase in which one of the capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator means and in which the other capacitor is biased with a reference voltage also selected in dependence on the digital output;
- and
- wherein said comparator means generates the digital output by comparison of the generated analog output voltage against a pair of thresholds, said thresholds being stretched outwardly from symmetrical thresholds centered at +/−¼ of the comparison range.
4 more elements
A bit-and-one-half analog to digital converter comprising:
- a switched capacitive sample and amplification circuit that accepts an analog input voltage and generates a multiplied analog output voltage;
- and
- a comparator which generates a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit;
- wherein said switched capacitive sample and amplification circuit samples the analog input voltage during a first sampling phase in which the voltage is stored on a plurality of capacitors, and generates the amplified analog output voltage during a second amplification phase in which at least one of the plurality of capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator and in which at least another one of the capacitors is biased with a reference voltage;
- and
- wherein said comparator generates the digital output by comparison of the generated analog output voltage against a plurality of thresholds.
3 more elements
A multi-stage pipelined analog to digital converter comprising:
- plural stages arranged in series relative to each other, each stage accepting an input analog voltage and generating a residual analog voltage together with a digital output;
- and
- a correction circuit for accepting the digital output from each of said plural stages and for generating a digital output in correspondence to an analog input voltage;
- wherein each stage comprises a switched capacitive sample and amplification circuit that accepts an analog input voltage and generates a multiplied analog output voltage and a comparator which generates a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit;
- wherein said switched capacitive sample and amplification circuit samples the analog input voltage during a first sampling phase in which the voltage is stored on a plurality of capacitors, and generates the amplified analog output voltage during a second amplification phase in which at least one of the plurality of capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator and in which at least another one of the capacitors is biased with a reference voltage;
- and
- wherein said comparator generates the digital output by comparison of the generated analog output voltage against a plurality of thresholds.
4 more elements
A bit-and-one-half analog to digital converter comprising:
- switched capacitive sample and amplification circuit means for accepting an analog input voltage and for generating a multiplied analog output voltage;
- and
- comparator means for generating a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit means;
- wherein said switched capacitive sample and amplification circuit means samples the analog input voltage during a first sampling phase in which the voltage is stored on a plurality of capacitors, and generates the amplified analog output voltage during a second amplification phase in which at least one of the plurality of capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator means and in which at least another one of the capacitors is biased with a reference voltage;
- and
- wherein said comparator means generates the digital output by comparison of the generated analog output voltage against a plurality of thresholds.
3 more elements
A multi-stage pipelined analog to digital converter comprising:
- plural stage means arranged in series relative to each other, each stage means for accepting an input analog voltage and for generating a residual analog voltage together with a digital output;
- and
- correction circuit means for accepting the digital output from each of said plural stage means and for generating a digital output in correspondence to an analog input voltage;
- wherein each stage means comprises a switched capacitive sample and amplification circuit means for accepting an analog input voltage and for generating a multiplied analog output voltage and a comparator means for generating a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit means;
- wherein said switched capacitive sample and amplification circuit means samples the analog input voltage during a first sampling phase in which the voltage is stored on a plurality of capacitors, and generates the amplified analog output voltage during a second amplification phase in which at least one of the plurality of capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator means and in which at least another one of said capacitors is biased with a reference voltage;
- and
- wherein said comparator means generates the digital output by comparison of the generated analog output voltage against a plurality of thresholds.
4 more elements
A method of converting an analog signal into a digital signal, comprising the steps of:
- (a) sampling an analog input during a sampling phase;
- (b) storing the analog input in a plurality of capacitors;
- (c) generating an amplified analog output voltage during an amplifying phase;
- (d) comparing the amplified analog output voltage with a plurality of threshold voltages;
- (e) switching at least one of the plurality of capacitors into a feedback arrangement in accordance with step (d);
- and
- (f) biasing at least another one of the plurality of capacitors with a reference voltage.
4 more elements
Dependencies are inferred from the claim text.