D/A conversion circuit and semiconductor device

A D/A conversion circuit, comprising:

• 2n gradation voltage lines, one of the 2n gradation voltage lines being selected according to an inputted n-bit (n is an integer not less than 2) digital signal, and a gradation voltage being supplied to an output line from the selected gradation voltage line;
• a circuit including a first circuit with n P-channel TFTs connected in series to each other and a second circuit with n N-channel TFTs connected in series to each other, the circuit including the first circuit and the second circuit connected in series to each other and being connected in parallel to each of the 2n gradation voltage line;
• and
• a connection portion between the first circuit and the second circuit, the connection portion being connected to the output line,
• wherein the digital signal is supplied to gate electrodes of the n P-channel TFTs and gate electrodes of the n N-channel TFTs connected to each of the 2n gradation voltage lines.

A D/A conversion circuit, comprising:

• 2n gradation voltage lines, one of the 2n gradation voltage lines being selected according to an inputted n-bit (n is an integer not less than 2) digital signal, and a gradation voltage being supplied to an output line from the selected gradation voltage line;
• a circuit including a first circuit with n P-channel TFTs connected in series to each other and a second circuit with n N-channel TFTs connected in series to each other, the circuit including the first circuit and the second circuit connected in series to each other and being connected in parallel to each of the 2n gradation voltage lines;
• and
• a connection portion between the first circuit and the second circuit, the connection portion being connected to the output line, wherein:
• voltages supplied to the 2n gradation voltage lines become high in a direction from the first gradation voltage line to the 2n-th gradation voltage line;
• the x-th (1≦x≦2n;
• x is an integer) gradation voltage line and the (2n+1−x)-th gradation voltage line are paired and are adjacent to each other;
• an arrangement of the first circuit and the second circuit is reversed between the paired gradation voltage lines;
• and
• the digital signal is supplied to gate electrodes of the n P-channel TFTs and gate electrodes of the n N-channel TFTs connected to each of the 2n gradation voltage lines.

A D/A conversion circuit in which a gradation voltage corresponding to an inputted n-bit (n is a natural number not less than 2) digital signal is supplied to an output line, characterized in that:

• the n-bit digital signal is divided into upper x bits and lower y bits (x+y=n;
• both x and y are natural numbers);
• adjacent two gradation voltage lines are selected from (2x+1) gradation voltage lines by the upper x bits of the n-bit digital signal;
• 2y gradation voltages are generated from gradation voltages of the two selected adjacent gradation voltage lines;
• and
• a corresponding gradation voltage is supplied to the output line from the 2y gradation voltages by the lower y bits of the n-bit digital signal.

A D/A conversion circuit in which a gradation voltage corresponding to an inputted n-bit (n is a natural number not less than 2) digital signal is supplied to an output line, characterized in that:

• the n-bit digital signal is divided into upper x bits and lower y bits (x+y=n;
• both x and y are natural numbers);
• a z-th gradation voltage line and a (z+1)-th gradation voltage line (1≦z≦2x;
• z is a natural number) are selected from (2x+1) gradation voltage lines by the upper x bits of the n-bit digital signal, voltages supplied to the gradation voltage lines becoming high in a direction from the first gradation voltage line to the (2x+1)-th gradation voltage line;
• 2y gradation voltages are formed from gradation voltages of the selected z-th and (z+1)-th gradation voltage lines;
• and
• a corresponding gradation voltage from the 2y gradation voltages is supplied to the output line by the lower y bits of the n-bit digital signal.

A semiconductor device, comprising;

• a plurality of TFTs disposed in matrix;
• a source signal line side driving circuit for driving the plurality of TFTs;
• and
• a gate signal line side driving circuit for driving the plurality of TFTs, wherein:
• the source signal line side driving circuit includes a D/A conversion circuit in which a gradation voltage corresponding to an inputted n-bit (n is a natural number not less than 2) digital signal is supplied to an output line;
• the n-bit digital signal is divided into upper x bits and lower y bits (x+y=n;
• both x and y are natural numbers);
• adjacent two gradation voltage line are selected from (2x+1) gradation voltage lines by the upper x bits of the n-bit digital signal;
• 2y gradation voltage lines are formed from gradation voltages of the two selected adjacent gradation voltage lines;
• and
• a corresponding gradation voltage from the 2y gradation voltages is supplied to the output line by the lower y bits of the n-bit digital signal.

A semiconductor device, comprising:

• a plurality of TFTs disposed in matrix;
• a source signal line side driving circuit for driving the plurality of TFTs;
• and
• a gate signal line side driving circuit for driving the plurality of TFTs, wherein:
• the source signal line side driving circuit includes a D/A conversion circuit in which a gradation voltage corresponding to an inputted n-bit (n is a natural number not less than 2) digital signal is supplied to an output line;
• the n-bit digital signal is divided into upper x bits and lower y bits (x+y=n;
• both x and y are natural numbers);
• a z-th gradation voltage line and a (z+1)-th gradation voltage line (1≦z≦2x;
• z is a natural number) are selected from (2x+1) gradation voltage lines by the upper x bits of the n-bit digital signal, voltages supplied to the gradation voltage lines becoming high in a direction from the first gradation voltage line to the (2x+1)-th gradation voltage line;
• 2y gradation voltages are formed from gradation voltages of the selected z-th and (z+1)-th gradation voltage lines;
• and
• a corresponding gradation voltage from the 2y gradation voltages is supplied to the output line by the lower y bits of the n-bit digital signal.

A semiconductor device, comprising:

• a plurality of TFTs;
• a source signal line side driving circuit for driving the plurality of TFTs;
• and
• a gate signal line side driving circuit for driving the plurality of TFTs, wherein:
• the source signal line side driving circuit includes a D/A conversion circuit in which a gradation voltage corresponding to an inputted n-bit (n is a natural number not less than 2) digital signal is supplied to an output line;
• the n-bit digital signal is divided into upper x bits and lower y bits (x+y=n;
• both x and y are natural numbers);
• a z-th gradation voltage line and a (z+1)-th gradation voltage line (1≦z≦2x;
• z is a natural number) are selected from the (2x+1) gradation voltage lines by the upper x bits of the n-bit digital signal, voltages supplied to the gradation voltage lines becoming high in a direction from the first gradation voltage line to the (2x+1)-th gradation voltage line;
• 2y gradation voltages are formed from gradation voltages of the selected z-th and (z+1)-th gradation voltage lines;
• and
• a corresponding gradation voltage from the 2y gradation voltages is supplied to the output line by the lower y bits of the n-bit digital signal.

A semiconductor device having a pixel region and a peripheral circuit region over a substrate, said peripheral circuit region having a D/A converter for n-bit digital signal comprising:

• 2n gradation voltage lines;
• n P-ch TFTs connected in series to each other;
• n N-ch TFTs connected in series to each other;
• and
• output line connected to a connection portion between n P-ch TFTs and n N-ch TFTs.

A semiconductor device having a pixel region and a peripheral circuit region over a substrate, said peripheral circuit region having a D/A converter for n-bit digital signal comprising:

• 2n gradation voltage lines;
• n P-ch TFTs connected in series to each other;
• n N-ch TFTs connected in series to each other;
• and
• output line connected to a connection portion between n P-ch TFTs and n N-ch TFTs,
• wherein said n P-ch TFTs and n N-ch TFTs are connected in series each other.

A semiconductor device having a pixel region and a peripheral circuit region over a substrate, said peripheral circuit region having a D/A converter for n-bit digital signal comprising:

• 2n gradation voltage lines;
• n P-ch TFTs connected in series to each other;
• n N-ch TFTs connected in series to each other;
• and
• output line connected to a connection portion between n P-ch TFTs and n N-ch TFTs,
• wherein said n P-ch TFTs and n N-ch TFTs are connected in series each other and in parallel to each of said 2n gradation voltage lines.

A method for driving a D/A converstion circuit for n-bit (n is a natural number not less than 2) digital signal, comprising the steps of:

• dividing the n-bit digital signal into upper x bits and lower y bits (x+y=n;
• both x and y are natural numbers);
• selecting adjacent two gradation voltage lines from (2x+1) gradation voltage lines by the upper x bits of the n-bit digital signal;
• generating 2y gradation voltages from gradation voltages of the two selected adjacent gradation voltage lines;
• and
• supplying a corresponding gradation voltage to an output line from the 2y gradation voltages by the lower y bits of the n-bit digital signal.

A method for driving a D/A conversion circuit for n-bit (n is a natural number not less than 2) digital signal, comprising the steps of:

• dividing the n-bit digital signal into upper x bits and lower y bits (x+y=n;
• both x and y are natural numbers);
• selecting a z-th gradation voltage line and a (z+1)-th gradation voltage line (1≦z≦2x;
• z is a natural number) from (2x+1) gradation voltage lines by the upper x bits of the n-bit digital signal, voltages supplied to the gradation voltage lines becoming high in a direction from the first gradation voltage line to the (2x+1)-th gradation voltage line;
• generating 2y gradation voltages from gradation voltages of the selected z-th and (z+1)-th gradation voltages lines;
• and
• supplying a corresponding gradation voltage from the 2y gradation voltages to the output line by the lower y bits of the n-bit digital signal.