US 6,441,691 B1 · PLL cycle slip compensation

Abstract

Phase-reset circuits provide first and second frequency-divided input signals to a phase/frequency detector (PFD) used in a phase-locked loop (PLL). The phase-reset circuits receive first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD generates control signals based on the phase difference between the frequency-divided input signals. Normally, the phase-reset circuits frequency divide the first and second input signals using divisors N and M, respectively. If other circuitry detects that the PFD has missed a clock cycle in the first or second clock-divided input signals, the corresponding phase-reset circuit alters its divider so that the next clock edge on the corresponding input signal clocks through to the PFD. This causes the PFD to quickly set its affected control signal to what it would have been had the clock cycle not been missed.

Claims41

Dependent claims

A phase detector for use in a PLL comprising:

first and second input circuits to generate first and second PLL control signals responsive to clock edges in first and second input signals, respectively;
a reset circuit to generate a reset pulse based on said first and second PLL control signals to reset said first and second input circuits, thereby clearing said first and second PLL control signals;
a first frequency divider providing said first input signal to said first input circuit, said first frequency divider responsive to a first cycle slip indicator signal to advance a next clock edge in said first input signal;
and
a second frequency divider providing said second input signal to said second input circuit, said second frequency divider responsive to a second cycle slip indicator signal to advance a next clock edge in said second input signal;
wherein said first cycle slip indicator signal indicates that said phase detector missed a clock edge in said first input signal, and said second cycle slip indicator indicates that said phase detector missed a clock edge in said second input signal.

3 more elements

A phase-locked loop (PLL) comprising:

a phase detector to generate first and second PLL control signals based on a detected phase difference between respective clock edges in first and second input signals, said phase detector comprising:
first and second input circuits to generate first and second PLL control signals responsive to clock edges in first and second input signals, respectively;
a reset circuit to generate a reset pulse based on said first and second PLL control signals to reset said first and second input circuits, thereby clearing said first and second PLL control signals;
a first frequency divider providing said first input signal to said first input circuit, said first frequency divider responsive to a first cycle slip indicator signal to advance a next clock edge in said first input signal;
and
a second frequency divider providing said second input signal to said second input circuit, said second frequency divider responsive to a second cycle slip indicator signal to advance a next clock edge in said second input signal;
and
a control circuit to generate a control signal based on said first and second PLL control signals;
and
a controllable oscillator to generate an output signal at a frequency based on said control signal.

7 more elements

A radio frequency transceiver comprising:

a receiver to receive a remotely transmitted signal at a receive frequency;
a transmitter to generate a transmit signal at a carrier frequency;
and
a frequency synthesizer to generate a first output signal bearing on said receive frequency and a second output signal bearing on said carrier frequency, said frequency synthesizer comprising:
a reference clock circuit to generate a reference clock signal;
and
first and second phase-locked loops (PLLs) to generate said first and second output signals, respectively, at least one of said PLLs comprising:
a phase detector to generate first and second PLL control signals based on a detected phase difference between respective clock edges in first and second input signals, said first input signal derived from said reference clock signal and said second input signal derived from a corresponding one of said first and second output signals, said phase detector comprising:
first and second input circuits to generate first and second PLL control signals responsive to clock edges in first and second input signals, respectively;
a reset circuit to generate a reset pulse based on said first and second PLL control signals to reset said first and second input circuits, thereby clearing said first and second PLL control signals;
a first frequency divider providing said first input signal to said first input circuit, said first frequency divider responsive to a first cycle slip indicator signal to advance a next clock edge in said first input signal;
and
a second frequency divider providing said second input signal to said second input circuit, said second frequency divider responsive to a second cycle slip indicator signal to advance a next clock edge in said second input signal;
and
a control circuit to generate a control signal based on said first and second PLL control signals;
and
a controllable oscillator to generate said corresponding one of said first and second output signals at a frequency based on said control signal.

14 more elements

A method of compensating for cycle slip in a PLL, the method comprising:

generating one clock pulse in a first input signal for every M clock pulses in a reference clock signal using a first frequency divider;
generating one clock pulse in a second input signal for every N clock pulse in an output signal of PLL using a second frequency divider;
advancing a current count value of said first frequency divider in response to a first cycle slip indicator signal to reduce the time before generating a next clock pulse in said first input signal;
and
advancing a current count value of said second frequency divider in response to a second cycle slip indicator to reduce the time before generating a next clock pulse in said second input signal.

2 more elements

Dependencies are inferred from the claim text.

PLL cycle slip compensation

Life of this patent

PLL cycle slip compensation

Life of this patent

Abstract

Claims41