Amplifier bias voltage generating circuit and method

An amplifier circuit comprising:

• an amplifying transistor having a base terminal coupled to an input signal source, an emitter terminal coupled to ground and a collector terminal coupled to an amplifier output node;
• and
• a bias voltage generating circuit having a bias output terminal coupled to the base terminal of the amplifying transistor, the bias voltage generating circuit being operable to generate a bias voltage at the base terminal of the amplifying transistor, the bias voltage generating circuit including:
• a first transistor having a base terminal coupled to the bias output terminal and an emitter terminal coupled to ground;
• a first resistor having a first terminal coupled to a supply voltage node, the first resistor having a second terminal coupled to a collector terminal of the first transistor;
• a second transistor having an emitter terminal coupled to the collector terminal of the first transistor, the second transistor having a base terminal connected to the collector terminal of the second transistor;
• and
• a second resistor having a first terminal coupled to the supply voltage node, the second resistor having a second terminal coupled to a collector terminal of the second transistor;
• a third transistor having a base terminal coupled to the base terminal of the second transistor, the third transistor having a collector terminal coupled to the supply voltage node, the third transistor having an emitter terminal coupled to the bias output terminal.

A method for amplifying an RF input signal, comprising:

• providing a supply voltage to a first terminal of a first resistor, the first resistor having a second terminal coupled to a collector terminal of a first transistor;
• providing the supply voltage to a first terminal of a second resistor, the second resistor having a second terminal connected to a collector terminal of a second transistor, the second transistor having an emitter terminal coupled to the collector terminal of the first transistor, the second transistor having a base terminal connected to the collector terminal of the second transistor;
• providing the supply voltage to a collector terminal of a third transistor, the third transistor having a base terminal connected to the base terminal of the second transistor, the third transistor having an emitter terminal coupled to the base terminal of the first transistor;
• generating a bias voltage by the third transistor at the emitter terminal of the third transistor;
• supplying the bias voltage to a bias node coupled to a base terminal of an amplifying transistor;
• supplying the RF input signal to an input node coupled to the base terminal of the amplifying transistor;
• and
• amplifying the RF input signal by the amplifying transistor.