CMOS voltage reference
AssigneeThe Hong Kong University of Science and Technology
InventorsKa Nang Leung, Kwok Tai Philip Mok, Ka Chun Kwok
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Abstract
A CMOS reference voltage generating circuit is described that produces a reference voltage by taking the difference between the gate-source voltages of two p-type and n-type CMOS transistors operating in the saturation region, one of the gate-source voltages being multiplied by a gain factor. Different circuits are described for situations where the n- or p-type transistors have the greater temperature dependence.
Claims19
A circuit for generating a reference voltage comprising a p-type CMOS transistor and an n-type CMOS transistor, said CMOS transistors being operated in the saturation region, and wherein the reference voltage is obtained from the difference between the gate-source voltage of the p- and n-type CMOS transistors with a gain factor greater than or less than 1 being applied to the gate-source voltage of either the p- or n-type CMOS transistor such that the reference voltage is given by the equation:
- Vref=k1·VGSn−k2·|VGSp| where either k1 or k2 is the gain factor and the other is unity.
Dependencies are inferred from the claim text.