5V-tolerant receiver for low voltage CMOS technologies

A method for preventing current leakage in a semiconductor integrated circuit device for receiving high voltage input signals, comprising:

• a) providing a pass gate device having a first input for receiving input logic voltages, a gate input connected to a first voltage supply source, and an output connected to a first node, said pass gate passing the received input voltage to said first node and providing high voltage protection for said receiver by limiting a high voltage passed to said first node;
• b) providing a first inverter device having a connection to a second voltage supply source, a connection to ground, and an output defining a second node, for pulling down said input voltage for output at said second node when said input voltage is high, and pulling up said input voltage to said limited voltage level for output at said second node when said input voltage switches to a low voltage;
• c) providing a first transistor device for connecting said first inverter device to said second voltage supply source;
• and,
• d) responding to said pulled down voltage at said second node for turning off said first transistor device for preventing leakage current to ground through said first inverter device, and enabling activation of said first transistor device to facilitate pulling up voltage at said second node via said inverter device when said input voltage transitions from low to high,
• wherein stable switching voltages is achieved at said second node in a manner that eliminates leakage current between said second voltage supply source and a receiver input.

A receiver circuit for interfacing a legacy system sourcing logic signals including high logic level signals at first voltage levels to semiconductor integrated circuit devices operating at second voltage levels, wherein the first voltage levels are greater than the second voltage levels, said receiver circuit comprising:

• a pass gate device receiving said input voltages including high level logic signals at first logic levels and translating said high logic level signals to an intermediate voltage level for output at a first circuit node, said intermediate voltage level being less than said first voltage level;
• a first inverter device for receiving said translated voltages at said intermediate voltage levels and inverting said voltages for output at a second circuit node, whereby high input logic level voltages are pulled down at said second node and low input logic level voltages are pulled up at said second node;
• a circuit element in series with said first inverter device for connecting said first inverter device to a voltage supply source that provides pulled up signals at said second voltage levels in response to low logic level input voltages;
• and,
• circuit means responsive to pulled down voltage at said second node for deactivating said first circuit element to thereby prevent leakage current to ground through said first inverter device, and responsive to pulled up voltage at said second node for enabling activation of said circuit element to facilitate pulling up voltage at said second node,
• wherein stable switching voltages is achieved at said second node in a manner that eliminates leakage current between the voltage supply source providing pulled up signals at said second voltage levels and the receiver input.

A method for preventing leakage current in a receiver circuit providing interface between a legacy system sourcing logic signals including high logic level signals at first voltage levels to semiconductor integrated circuit devices operating at second voltage levels, wherein the first voltage levels are greater than the second voltage levels, said method comprising the steps of:

• a) receiving said input voltages including high level logic signals at first logic levels and translating said high logic level signals to an intermediate voltage level for output at a first circuit node, said intermediate voltage level being less than said first voltage level;
• b) receiving said translated voltages at said intermediate voltage level and inverting said voltages for output at a second circuit node, whereby high input logic level voltages are pulled down at said second node and low input logic level voltages are pulled up at said second node;
• c) providing a circuit element device in series with said first inverter device for connecting said first inverter device to a voltage supply source providing pulled up signals at said second voltage levels;
• d) responding to pulled down voltage at said second node for deactivating said first circuit element to thereby prevent leakage current to ground through said first inverter device, and responding to pulled up voltage at said second node for enabling activation of said first circuit element to facilitate pulling up voltage at said second node,
• wherein stable switching voltages is achieved at said second node in a manner that eliminates leakage current between the voltage supply source and the receiver input.