Multiphase clock generator
AssigneeInternational Business Machines Corporation
InventorsDavid William Boerstler, Robert Keven Montoye, Kevin John Nowka
Life of this patent
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Abstract
The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate a control voltage which controls the frequency of the MVCO and to-generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.
Claims30
An apparatus for generating K-phases of a multiple phase clock (MPCK), said MPCK having a frequency F corresponding to a reference clock of frequency F, said apparatus comprising:
- a voltage controlled oscillator:
- with M-phase outputs (MPVCO), said M-phase outputs having frequency J set in response to a control voltage;
- an M-phase detector (MPD) receiving said reference clock and said M-phase outputs of said MPVCO, said MPD generating M-detector outputs in response to said M-phase outputs and said reference clock;
- a Sync State logic circuit receiving said M-detector outputs of said MPD, said Sync State logic circuit generating a Sync State output and an error signal, said error signal processed by a citcuit to generate said control voltage for said MPVCO;
- and
- a multiple phase clock logic circuit (MPCL) receiving said M-phase outputs of said MPVCO, said MPCL generating said K-phases of said MPCK.
An integrated circuit (IC) for generating K-phases of a multiple phase clock (MPCK), said MPCK having a frequency F corresponding to a reference clock of frequency F, said IC comprising:
- a voltage controlled oscillator with M-phase outputs (MPVCO), said M-phase outputs having frequency J set in response to a control voltage;
- an M-phase detector (MPD) receiving said reference clock and said M-phase outputs of said MPVCO, said MPD generating M-detector outputs in response to said M-phase outputs and said reference clock;
- a Sync State logic circuit receiving said M-detector outputs of said MPD, said Sync State, logic circuit generating a Sync State output and an error signal, said error signal processed by a circuit to generate said control voltage for said MPVCO;
- and
- a multiple phase clock logic circuit (MPCL) receiving said M-phase outputs of said MPVCO, said MPCL generating said K-phases of said MPCK.
A method for generating K-phases of a multiple phased clock (MPCK), said MPCK having a frequency F corresponding to a reference clock of frequency F, said method comprising the steps of:
- generating in a multiple phased output voltage controlled oscillator (MPVCO) M-phases of a frequency J equal to F×N set in response to a control voltage wherein N is greater than one;
- sampling and latching states of said M-phase outputs of said MPVCO with edges of said reference clock generating sampled phase outputs;
- generating M-detector outputs in response to said sampled phase outputs and said reference clock;
- generating a Sync State output by combining in a logic circuit selected ones of said M-detector outputs;
- generating an error signal in response to said Sync State output, said error signal processed to generate said control voltage for said MPVCO;
- and
- generating said K-phases of said reference clock by dividing said M-phase outputs in sequential logic gates.
Dependencies are inferred from the claim text.