US 6,441,665 B1Granted

Semiconductor integrated circuit

AssigneeOki Electric Industry Co., Ltd.

InventorsShuichi Hashidate, Shinichi Fukuzako, Tetsuya Tanabe

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Abstract

A semiconductor integrated circuit is provided that achieves a lesser degree of inconsistency in the delay time of clock signals that are internally provided. An input clock signal distributed via an input clock supply path is provided to individual timing adjustments circuits. The timing adjustment circuits are each constituted by providing a wiring pattern having serial resistors and gaps in a circuit correction area. The wiring pattern of the semiconductor integrated circuit is corrected by employing a focused ion beam apparatus to achieve an adjustment so that internal input clock signals at the same phase are obtained from the individual timing adjustment circuits. Using the wiring pattern having undergone the adjustment, a semiconductor integrated circuit is manufactured as a product.

Claims14

Dependent claims

A semiconductor integrated circuit, comprising:

a plurality of input terminals to which input data with a plurality of bits are provided in parallel with uniform timing;
an input clock terminal to which an input clock signal indicating timing of the input data is provided;
a plurality of input data holding circuits, each connected to respective ones of said plurality of input terminals, that hold the input data provided to said input terminals based on timing of a rise or a fall of an internal input clock signal;
an input clock distributor that distributes the input clock signal provided to said input clock terminal;
and
a plurality of adjustable input clock suppliers, each provided between said input clock distributor and respective ones of said input data holding circuits, that generate the internal input clock signals with uniform timing in synchronization with the input data to be provided to said input data holding circuits, by circuit elements that are selectively connectable and disconnectable to correct differences in delay time of said input clock signal occurring in different distribution routes at said input clock distributor.

3 more elements

A semiconductor integrated circuit, comprising:

a plurality of input terminals to which input data with a plurality of bits are provided in parallel with uniform timing;
an input clock terminal to which an input clock signal indicating timing of the input data is provided;
a plurality of input data holding circuits, each connected to respective ones of said plurality of input terminals, that hold the input data provided to said input terminals based on timing of a rise or fall of an internal input clock signal;
an input clock distributor that distributes said input clock signal provided to said input clock terminal;
a plurality of input clock suppliers, each provided between said input clock distributor and respective ones of said input data holding circuits, that provide the internal input clock signals generated based upon said input clock signal distributed by said input clock distributor to said input data holding circuits;
a plurality of output terminals that output in parallel output data with a plurality of bits;
an output clock terminal provided with an output clock signal indicating timing with which the output data are output;
a plurality of output data holding circuits, each connected to respective ones of said plurality of output terminals, that output the output data to said output terminals based on an internal output clock signal;
an output clock distributor that distributes said output clock signal provided to said output clock terminal;
a plurality of output clock suppliers, each provided between said output clock distributor and respective ones of said output data holding circuits, that generate the internal output clock signals based upon said output clock signal distributed by said output clock distributor to be provided to said output data holding circuits;
and
a plurality of data loop-back circuits that each provide input data held at respective ones of said input data holding circuits to respective ones of said output data holding circuits as output data, when a test mode is specified by a mode signal that specifies either said test mode or a normal mode.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/592,261Filed 12 Jun 2000
Priority: JP 11-33407825 Nov 1999
Granted: 27 Aug 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03K 5/13
Manipulating of pulses not covered by one of the other main groups of this subclass: arrangements having a single output and transforming input…
G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
H03K 5/15013
Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors: with more than two outputs
H03K 19/00323
Modifications for increasing the reliability for protection: delay compensation