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AssigneeInternational Business Machines Corporation
InventorsChing-Te Kent Chuang, Jente Benedict Kuang
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A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) Schmitt trigger circuit with controllable hysteresis and a method are provided for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications. A SOI CMOS Schmitt trigger circuit with controllable hysteresis includes a stack of a plurality of field effect transistors (FETs) connected in series between a voltage supply and ground. An input is applied to a gate of each of the stack of the plurality of field effect transistors (FETs). The stack of the plurality of field effect transistors (FETs) provides an output at a junction of a predetermined pair of the plurality of field effect transistors (FETs). At least one feedback field effect transistor (FET) has a source coupled a junction of a predefined pair of the stack of field effect transistors (FETs) and has a gate coupled to the output. A FET body of each of the stack of the plurality of field effect transistors (FETs) is connected to a voltage supply rail. The stack of the plurality of field effect transistors (FETs) includes a plurality of P-channel field effect transistors (PFETs) and a plurality of N-channel field effect transistors (NFETs). The FET body of each of the plurality of P-channel field effect transistors (PFETs) is connected to a positive voltage supply rail and the FET body of each of the plurality of N-channel field effect transistors (NFETs) is connected to a voltage supply ground rail. The FET body of a P-channel feedback field effect transistor (PFET) is connected to one of a positive voltage supply rail, the gate or the source of the feedback PFET. The FET body of a N-channel feedback field effect transistor (NFET) is connected to one of a voltage supply ground rail, the gate or the source of the feedback NFET. A successive switching threshold adjustment technique is provided. Additional successive switching threshold adjustment is achieved by successive tapping of NFET or PFET feedback devices for the V+ or the V− trigger edges, respectively. With this arrangement, higher V+ and lower V− are realized without using excessively wide NFET or PFET feedback devices.
A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) Schmitt trigger circuit with controllable hysteresis comprising:
A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) Schmitt trigger circuit with controllable hysteresis comprising:
A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) Schmitt trigger circuit with controllable hysteresis comprising:
A method for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications, the SOI CMOS Schmitt trigger circuit including a stack of a plurality of P-channel and N-channel field effect transistors (PFETs and NFETs) connected in series between a voltage supply and ground, each receiving a gate input and providing an output between a predetermined pair of the FETs;
A method for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications, the SOI CMOS Schmitt trigger circuit including a stack of a plurality of P-channel and N-channel field effect transistors (PFETs and NFETs) connected in series between a voltage supply and ground, each receiving a gate input and providing an output between a predetermined pair of the FETs;
A method for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications, the SOI CMOS Schmitt trigger circuit including a stack of a plurality of P-channel and N-channel field effect transistors (PFETs and NFETs) connected in series between a voltage supply and ground, each receiving a gate input and providing an output between a predetermined pair of the FETs;
Dependencies are inferred from the claim text.