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US 6,441,662 B2Granted
DLL circuit that can prevent erroneous operation
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorYutaka Ikeda
Life of this patent
Estimating the term…
Abstract
A DLL circuit includes a counter control circuit. The counter control circuit includes an inverter, a NAND gate, a shift register, a clocked inverter, and a NOR gate. When a reset signal RST of an H level, or a smallest address signal CMIN indicating the smallest value of the address is input, the counter control circuit forces a signal REV to be switched to an H level and generates a counter control signal ADD and a signal EN of an H level, whereby the counter enters a force up mode. As a result, the delay clock CLKD can be set in phase with a reference clock CLK stably.
Claims14
A DLL circuit comprising:
- a control clock generation circuit generating a first control clock according to a reference clock and a second control clock having a phase difference with respect to set first control clock;
- a phase comparator comparing a phase of a delay clock with the phase of the reference clock;
- a filter providing a control signal applied with weight corresponding to a comparison result of said phase comparator;
- a counter control circuit driven in synchronization with said first control clock to generate a counter control signal according to said control signal;
- a counter driven in synchronization with said second control clock to count up/down according to said counter control signal, providing first and second addresses and a smallest address signal that is rendered active when said first and second addresses take the smallest values, and sets the address to the smallest value at a reset signal;
- a first delay circuit generating first and second signals having a phase difference of a predetermined amount according to said reference clock, and generating a fine adjustment clock whose phase is present between the phase of said first signal and the phase of said second signal according to said generated first and second signals and said first address;
- and
- a second delay circuit delaying said fine adjustment clock by an integral multiple of said predetermined amount to output said delay clock according to said second address;
- said counter control circuit providing a counter control signal rendered active to force said counter to count up when said reset signal is input, or when an activated smallest address signal and an output signal of said filter that causes said counter to count down are input.
6 more elements
A DLL circuit comprising:
- a control clock generation a first control clock according to a reference clock and a second control clock having a phase difference with respect to said first control clock;
- a phase comparator comparing a phase of a delay clock with the phase of the reference clock;
- a counter control circuit driven in synchronization with said first control clock to generate a counter control signal according to a control signal generated by a comparison result of said phase comparator;
- a counter driven in synchronization with said second control clock to count up/down according to said counter control signal, providing a count value as an address, and setting the address to a smallest value in response to a reset signal;
- and
- a delay circuit delaying said reference clock according to said address to output said delay clock;
- said counter control circuit providing a counter control signal rendered active to force said counter to count up when said reset signal is input.
4 more elements
A DLL circuit comprising:
- a control clock generation circuit generating a first control clock according to a reference clock and a second control clock having a phase difference with respect to said first control clock;
- a phase comparator comparing a phase of a delay clock with the phase of the reference clock;
- a counter control circuit driven in synchronization with said first control clock to generate a counter control signal according to a control signal generated by a comparison result of said phase comparator;
- a counter driven in synchronization with said second control clock to count up/down according to said counter control signal, providing a count value as an address, and providing a smallest address signal that is rendered active when said address takes the smallest value;
- and
- a delay circuit delaying said reference clock according to said address to output said delay clock;
- said counter control circuit providing a counter control signal rendered active to force said counter to count up when an activated smallest address signal and a control signal that causes said counter to count down are input.
4 more elements
Dependencies are inferred from the claim text.