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US 6,441,661 B1Granted
PLL circuit
AssigneesAsahi Kasei Kabushiki Kaisha, Asahi Kasei Microsystems Co., Ltd., Sony Corporation
InventorsHiroshi Aoki, Shiro Suzuki, Junichi Horigome, Takayoshi Chiba, Shigeo Yamaguchi
Life of this patent
Estimating the term…
Abstract
An A/D converter (30) samples an analog signal synchronously with a sampling clock from a VCO (70). These sampled values are stored in a shift register (410). A code judging section (420) detects the positive/negative sign pattern (time-series code pattern) of the sampled values held in storage elements (S0 to S5) of the shift register (410) and stores the sampled values in predetermined register (431 to 434) according to the detected sign pattern. According to this, a calculating section (430) determines the phase difference between the analog signal and the sampling clock. The phase difference is fed to a VCO (70) through a D/A converter (50) and a loop filter (60).
Claims14
A PLL circuit, comprising:
- an A/D converter for obtaining sampled values in turn by sampling an analog signal as well as synchronizing with a sampling clock;
- a phase difference detecting circuit for obtaining phase difference between said analog signal and said sampling clock on the basis of said sampled values received from the A/D converter;
- a loop filter for integrating said phase difference;
- and
- a voltage controlled oscillator for controlling the timing of said sampling clock according to said phase difference integrated,
- wherein said phase difference detection circuit obtains said phase difference according to a predetermined operational equation by using a predetermined number of sampled values, obtains a sign pattern of said predetermined number of sampled values, and determines input values to said operational equation according to this obtained sign pattern;
- and
- wherein said phase difference detecting circuit has a table that describes the relation between said sign patterns and input values to said operational equation, and determines input values to said operational equation by referring to said sign patterns and said table.
5 more elements
A PLL circuit, comprising:
- an A/D converter for obtaining sampled values in turn by sampling an analog signal as well as synchronizing with a sampling clock;
- a phase difference detecting circuit for obtaining phase difference between said analog signal and said sampling clock on the basis of said sampled values received from the A/D converter;
- a loop filter for integrating said phase difference;
- and
- a voltage controlled oscillator for controlling the timing of said sampling clock according to said phase difference integrated,
- wherein said phase difference detection circuit obtains said phase difference according to a predetermined operational equation by using a predetermined number of sampled values, obtains a sign pattern of said predetermined number of sampled values, and determines input values to said operational equation according to this obtained sign pattern;
- and
- wherein said phase difference detecting circuit comprises a register for storing sampled values from said A/D converter in turn;
- a code judging section that obtains a sign pattern of the predetermined number of sampled values stored in the register, and determines according to this sign pattern, which is obtained, whether processing contents are updated to predetermined sampled values as input values to said operational equation or not updated;
- and
- a calculating section for obtaining said phase difference according to said operational equation on the basis of the determination of the code judging section.
8 more elements
A PLL circuit, comprising:
- an A/D converter for obtaining sampled values in turn by sampling an analog signal as well as synchronizing with a sampling clock;
- a phase difference detecting circuit for obtaining phase difference between said analog signal and said sampling clock on the basis of said sampled values received from the A/D converter;
- a loop filter for integrating said phase difference;
- and
- a voltage controlled oscillator for controlling the timing of said sampling clock according to said phase difference integrated,
- wherein said phase difference detection circuit obtains said phase difference according to a predetermined operational equation by using a predetermined number of sampled values, obtains a sign pattern of said predetermined number of sampled values, and determines input values to said operational equation according to this obtained sign pattern;
- and
- wherein said phase difference detecting circuit comprises a first register for storing sampled values from said A/D converter in turn;
- a second register for storing a state corresponding to a sign pattern of sampled values stored in the first register;
- a code judging section for determining whether processing contents are to be updated in predetermined sampled values, stored in said first register, as input values to said operational equation according to a sign pattern of a predetermined number of newest sampled values stored in said first register and the state stored in said second register, or whether processing contents are not to be updated;
- and
- a calculating section for obtaining said phase difference according to said operational equation on the basis of the determination of the code judging section.
9 more elements
A PLL circuit, comprising:
- an A/D converter for obtaining sampled values in turn by sampling an analog signal as well as synchronizing with a sampling clock;
- a phase difference detecting circuit for obtaining phase difference between said analog signal and said sampling clock on the basis of said sampled values received from the A/D converter;
- a loop filter for integrating said phase difference;
- and
- a voltage controlled oscillator for controlling the timing of said sampling clock according to said phase difference integrated,
- wherein said phase difference detection circuit obtains said phase difference according to a predetermined operational equation by using a predetermined number of sampled values, obtains a sign pattern of said predetermined number of sampled values, and determines input values to said operational equation according to this obtained sign pattern;
- offset detecting means for detecting an offset of said analog signal by performing predetermined calculation for a plurality of sampled values outputted in turn from said A/D converter;
- and
- offset canceling means for generating a signal canceling an offset detected by this offset detecting means and supplying this signal to an input side of said A/D converter.
6 more elements
Dependencies are inferred from the claim text.